SAR ADC Top-Plate Sampling Layout for Better Linearity
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Solution Overview
Problem
Current successive approximation analogue-digital converters (SAR ADCs) using bottom plate sampling face limitations such as the need to route input to every capacitor, separate sampling switches for each capacitor, increased parasitic capacitance, and leakage from reference switches, which degrade sampling linearity.
Innovation Solution
A top plate sampling architecture for SAR ADCs, utilizing a capacitive DAC with a latched comparator and a single sampling switch, where reference switches hold the bottom plate at a common-mode and eliminate the need for separate switches on the top plate, reducing leakage and routing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bottom plate sampling is used in SAR ADC, then charge redistribution can be achieved, but routing complexity increases as input must be routed to every bottom plate capacitor
Solution Approach 1:
The patent inverts the conventional bottom-plate sampling approach by implementing top-plate sampling. Instead of routing input signals to every bottom plate capacitor, the input is routed to a single top plate sampling node. The sampling switch connects the input to the top plate, and charge redistribution occurs through the capacitor array connected to the bottom plate, eliminating the need for complex routing to each capacitor.
Solution Approach 2:
The top plate sampling node serves as a universal input point for all capacitors in the array. A single sampling switch and single input routing path provide charge to the entire capacitor array through the top plate, making the routing structure universal rather than requiring individual connections to each capacitor.
2Ease of operation
If separate sampling switches are used for each capacitor in bottom plate sampling, then individual capacitor control is achieved, but device complexity and parasitic capacitance increase
Solution Approach 1:
The patent merges the sampling function into a single switch located at the top plate sampling node. Instead of having separate sampling switches for each capacitor, one unified sampling switch controls the charge distribution to the entire capacitor array. This single switch performs the sampling function for all capacitors simultaneously, reducing the total number of switches while maintaining control capability.
3Reliability
If boosted gate-drive is routed to every sampling switch in bottom plate sampling, then switch operation is ensured, but parasitic capacitance on sampling network increases
Solution Approach 1:
The patent extracts the boosted gate-drive routing from the multiple individual switch locations and consolidates it to a single location at the top plate sampling switch. By having only one sampling switch instead of multiple switches, the number of gate-drive routes is reduced from many to one, thereby extracting and eliminating the excess parasitic capacitance associated with multiple gate-drive networks.
4Ease of operation
If reference switches are used in bottom plate sampling, then bottom plate voltage control is achieved, but leakage current degrades sampling linearity
Solution Approach 1:
The patent inverts the sampling location from bottom plate to top plate. By placing the sampling switch and input connection at the top plate rather than the bottom plate, the reference switches are no longer part of the sampling signal path. The bottom plate reference switches only control the reference voltages for the capacitors, not the sampling signal itself, thereby eliminating the leakage current that would otherwise degrade sampling linearity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances sampling linearity, reduces switch leakage, and simplifies the sampling process by minimizing the number of switches and parasitic capacitance, resulting in a more reliable and efficient ADC conversion.
Implementation Method 1
SAR ADC utilize bottom plate sampling for charge redistribution
Implementation Method 2
The latched comparator includes: a first metal oxide semiconductor field effect transistor (MOSFET) having a first source terminal and a first drain terminal
Data Source
AI summary
The present disclosure provides an analogue to digital converter (ADC) (100), which includes: a capacitive digital to analogue converter (DAC) (120) configured to sample and hold a received sampling input signal and a latched comparator (140) including a first metal oxide semiconductor field effect transistor (MOSFET) (202); a second MOSFET (204) connected in parallel to the first MOSFET; a third MOSFET (226), wherein a third source terminal of the third MOSFET (226) is coupled with first drain terminal and second drain terminal of the first and second MOSFET (202, 204), wherein a sampling switch (130) is configured to the third source terminal to selectively allow voltage to be supplied to the third MOSFET (226), and wherein the sampling switch is configured to disallow voltage to be supplied to the third MOSFET when the ADC is sampling the input signal.