Programmable Trim Filter in SAR ADC Comparators for Settling Time
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Solution Overview
Problem
Variations in CMOS fabrication processes result in microchips with different speeds, leading to settling time issues in SAR ADCs, where slow chips may produce erroneous data due to insufficient settling time, and increasing power to address this increases noise in both slow and fast chips, particularly undesirable in low-power applications.
Innovation Solution
A programmable trim filter network is introduced, comprising capacitors controlled by transistors, positioned between comparator preamplifiers and a latch, allowing adjustment of filter capacitance to optimize bandwidth, settling time, and noise based on microchip speed, with a process monitor and ring oscillator determining the optimal trim filter setting for each microchip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If power is increased to reduce settling time in slow chips, then settling time is improved, but noise increases in both slow and fast chips
Solution Approach 1:
The patent applies local quality by providing different bandwidth configurations to different chips based on their individual speed characteristics. Each chip is trimmed with a specific bandwidth value that matches its performance level, so fast chips receive low bandwidth (low noise) while slow chips receive high bandwidth (low settling time). This resolves the contradiction by making the noise level locally optimized for each chip rather than uniformly high across all chips.
Solution Approach 2:
The patent changes the bandwidth parameter of the comparator based on the chip's speed classification. By trimming the bandwidth to different values (high, medium, low) corresponding to slow, average, and fast chips respectively, the system achieves optimal settling time for each chip type without unnecessarily increasing noise. This parameter adjustment resolves the contradiction between settling time and noise.
2Loss of time
If bandwidth is increased to reduce settling time, then settling time is improved, but noise and power consumption increase
Solution Approach 1:
The patent applies local quality by matching the bandwidth (and thus power consumption) to the specific needs of each chip. Fast chips are configured with low bandwidth and consequently low power consumption, while only slow chips receive high bandwidth and high power consumption. This resolves the contradiction by ensuring that power consumption is locally optimized rather than uniformly high across all chips.
Solution Approach 2:
The patent changes the bandwidth parameter based on chip speed classification, which directly affects power consumption. By trimming bandwidth to appropriate levels for each chip type, the system achieves the minimum necessary power consumption for each chip's performance level, resolving the contradiction between settling time and power consumption.
3Loss of time
If bandwidth is increased to reduce settling time, then settling time is improved, but noise increases unnecessarily in fast chips
Solution Approach 1:
The patent applies local quality by providing different bandwidth configurations to different chips based on their individual speed characteristics. Each chip is trimmed with a specific bandwidth value that matches its performance level, so fast chips receive low bandwidth (low noise) while slow chips receive high bandwidth (low settling time). This resolves the contradiction by making the noise level locally optimized for each chip rather than uniformly high across all chips.
Solution Approach 2:
The patent applies partial action by providing only the necessary bandwidth to each chip based on its speed classification. Fast chips receive minimal bandwidth (partial action) sufficient for their fast settling characteristics, avoiding excessive bandwidth that would generate unnecessary noise. This resolves the contradiction by preventing excessive noise in fast chips while providing adequate bandwidth to slow chips.
Data Source
AI summary
The disclosure includes a successive approximation register (SAR) analog to digital converter (ADC). The SAR ADC includes a sampling network to store a sample of an analog signal. The SAR ADC also includes a comparator to successively compare the sample to reference values to determine a digital value corresponding to the sample of the analog signal. The comparator employs a plurality of comparator preamplifiers. The comparator also includes a programmable trim filter. The programmable trim filter is selectively set to adjust a bandwidth of the comparator preamplifiers to a bandwidth value corresponding with a preamplifier settling time subceeding a preamplifier settling threshold.