SAR ADC Sigma-Delta Modulator With Truncated Feedback Path
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Solution Overview
Problem
Conventional sigma-delta modulators face challenges in achieving high-speed operation and low power consumption while maintaining good noise performance, often resulting in complex circuit structures and stability issues due to high-order loop filters and multi-bit quantizers.
Innovation Solution
The proposed sigma-delta modulator employs a processing circuit, a successive approximation register (SAR) analog-to-digital converter (ADC) as a quantizer, and a feedback circuit with a first-order truncater, which reduces noise requirements and allows for a compact chip size and low power consumption by simplifying the circuit structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If high-order loop filters are used to enhance performance, then signal-to-noise ratio is improved, but stability issues arise and oscillation becomes unstable
Solution Approach 1:
The patent segments the quantization process into multiple stages: a multi-bit quantizer followed by a truncater. This segmentation allows the system to achieve high resolution through the multi-bit quantizer while the truncater simplifies the feedback path, preventing stability issues associated with high-order loop filters.
Solution Approach 2:
The patent extracts and removes the truncater component from the traditional sigma-delta modulator structure. This truncater takes out the least significant bits after quantization, effectively reducing the complexity of the feedback path while maintaining the resolution benefits of multi-bit quantization, thereby resolving the stability contradiction.
2Measurement precision
If multi-bit quantizers with increased bit number are employed to guarantee resolution boost, then measurement precision is improved, but device complexity increases and power consumption rises
Solution Approach 1:
The quantization output is segmented into two parts: the full multi-bit digital signal for high resolution, and a truncated version with fewer bits for feedback. This segmentation allows the system to enjoy the resolution benefits of multi-bit quantization while using a simpler truncated signal in the feedback path, reducing overall circuit complexity.
Solution Approach 2:
The truncater extracts only the necessary most significant bits from the multi-bit quantizer output for feedback purposes. This extraction reduces the bit width in the feedback path, thereby simplifying the DAC and associated circuitry while preserving the high-resolution capability of the full multi-bit output.
3Measurement precision
If multi-bit quantizers with increased bit number are used to achieve resolution boost, then measurement precision is improved, but power consumption increases
Solution Approach 1:
The signal path is segmented into a high-resolution multi-bit path and a lower-resolution truncated path. The multi-bit quantizer operates at full resolution, but the truncater creates a lower-bit version for feedback, reducing the power consumption of the feedback DAC and associated circuitry while maintaining high resolution in the final output.
Solution Approach 2:
The truncater extracts and removes the least significant bits from the quantizer output before feeding back to the integrator. This extraction reduces the power consumption of the feedback path by using fewer bits, while the full multi-bit signal is still available for the final high-resolution output.
4Measurement precision
If traditional integrator and truncater components are used, then noise performance is maintained, but device complexity increases and chip area expands
Solution Approach 1:
The patent merges the integrator and truncater functions into a unified structure where the truncater operates directly on the quantizer output and feeds back to the integrator input. This merging eliminates the need for separate, bulky implementations of each component, reducing chip area while maintaining the noise-shaping benefits of the integrator and the resolution benefits of the truncater.
Data Source
AI summary
A sigma-delta modulator includes a processing circuit, a quantizer, a truncater and a feedback circuit. The processing circuit receives an input signal and an analog information and generates an integrated signal by perform an integration upon a difference between the input signal and the analog information. The quantizer includes a successive approximation register (SAR) analog-to-digital converter (ADC) for receiving the integrated signal and generating a digital information according to the integrated signal. The truncater receives the digital information and generates a truncated information according to the digital information. The feedback circuit generates the analog information to the processing circuit according to the truncated information.