SAR ADC Variable LSB Quantization for Faster Low-Power Conversion
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Solution Overview
Problem
Conventional successive approximation register (SAR) analog-to-digital converters (ADCs) with fixed least significant bit (LSB) sizes are inefficient in terms of power dissipation and maximum sampling rate, as they perform a fixed number of comparisons regardless of the analog input signal amplitude.
Innovation Solution
A SAR ADC circuit with a variable quantization size of LSB, where the LSB size depends on the amplitude of the analog input signal, allowing for fewer comparisons and thus higher sampling rates or lower power dissipation by adjusting the quantization size based on the input signal amplitude.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a fixed LSB size is used in SAR ADC, then the conversion accuracy is maintained consistently, but the power dissipation increases and maximum sampling rate decreases
Solution Approach 1:
The patent implements a variable LSB size that dynamically adjusts based on the amplitude of the input signal. The SAR ADC switches between different quantization precision levels (e.g., full precision for small signals, reduced precision for large signals), making the conversion accuracy adaptive rather than fixed. This dynamic adjustment reduces the number of comparison iterations needed for large-amplitude signals, thereby lowering power consumption while maintaining adequate accuracy for the given signal range.
2Device complexity
If a fixed LSB size is used in SAR ADC, then the conversion process is simplified, but the maximum sampling rate is limited
Solution Approach 1:
The patent applies partial precision conversion by using full LSB precision only when necessary (for small-amplitude signals), and reducing to partial precision for large-amplitude signals. This means the ADC performs fewer comparison iterations than the maximum possible, executing only the necessary amount of conversion work required for each specific input signal, thereby increasing sampling rate without excessively complicating the conversion process.
3Productivity
If variable LSB size is implemented in SAR ADC, then power dissipation is reduced and sampling rate increases, but the device complexity increases
Solution Approach 1:
The patent segments the signal amplitude range into multiple zones (e.g., small-amplitude zone requiring full precision, large-amplitude zone allowing reduced precision). The ADC circuit is divided into multiple operational modes with different quantization precision levels. This segmentation allows the system to switch between predetermined precision levels based on signal characteristics, managing complexity through structured zoning rather than continuous variable precision.
Solution Approach 2:
The patent changes the quantization parameter (LSB size) based on the input signal amplitude. By adjusting this key parameter dynamically or semi-dynamically, the ADC achieves variable precision conversion. The logic circuit modifies the effective resolution or number of comparison iterations based on detected signal amplitude, allowing productivity improvement through parameter adaptation while controlling complexity through systematic parameter management.
Data Source
AI summary
Techniques and apparatus for successive approximation register (SAR) analog-to-digital converters (ADCs) with variable resolution. One example SAR ADC is generally configured to convert an analog input signal to a digital output signal, wherein a quantization size of a least significant bit (LSB) associated with the digital output signal is configured to depend on an amplitude of the analog input signal. By utilizing the techniques and apparatus described herein, a SAR ADC may be capable of a higher maximum sampling rate or a lower power dissipation.