SAR ADC Voltage-Domain Segmentation for Faster Conversion
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Solution Overview
Problem
High-speed successive approximation register (SAR) analog-to-digital converters face challenges with slow conversion times due to high voltage control logic, increased capacitance, and the need for multiple reference voltage pins, which lead to increased package size, power consumption, and propagation delays.
Innovation Solution
The implementation of a single reference voltage pin for multiple SAR ADCs using a high voltage buffer for bits of higher significance and a low voltage buffer for bits of lower significance, eliminating the need for level shifters and reducing circuit area and power consumption, while operating most circuitry in a low voltage domain to minimize propagation delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high voltage control logic is used for SAR ADC operation, then the converter can achieve high speed conversion, but the propagation delays and power consumption increase
Solution Approach 1:
The patent segments the control logic into two distinct domains: high voltage control logic for significant bits and low voltage control logic for less significant bits. This segmentation allows each domain to operate at its optimal voltage level, reducing overall power consumption while maintaining conversion speed. The high voltage domain handles only the most critical bits requiring faster switching, while the low voltage domain handles remaining bits with lower power requirements.
Solution Approach 2:
The patent applies local quality by assigning different voltage characteristics to different parts of the control logic based on their functional requirements. The significant bit control logic operates at high voltage for speed-critical operations, while the less significant bit control logic operates at low voltage for power-efficient operations. This localized optimization resolves the contradiction between speed and power consumption.
2Reliability
If multiple reference voltage pins are used for high voltage operation, then the ADC can function properly, but the package size and cost increase
Solution Approach 1:
The patent makes a single reference voltage pin serve multiple functions by using it for both high voltage reference and low voltage reference through voltage division. This multi-functionality eliminates the need for separate reference pins for different voltage domains, reducing package size and cost while maintaining full ADC functionality. The same physical pin provides reference voltage to both high voltage and low voltage control logic through appropriate voltage division networks.
3Adaptability or versatility
If level shifters are added for voltage domain conversion, then multiple voltage domains can be supported, but the circuit area and propagation delay increase
Solution Approach 1:
The patent extracts the voltage conversion function from traditional level shifter circuits and replaces it with passive voltage division networks. By removing the active level shifter components and using simple resistive dividers to generate appropriate reference voltages for different domains, the circuit area is significantly reduced while maintaining voltage domain compatibility. This extraction eliminates complex voltage conversion circuitry while preserving the ability to support multiple voltage domains.
4Stability of the object's composition
If high voltage control logic is used throughout the SAR ADC, then uniform operation is achieved, but power consumption and propagation delay increase
Solution Approach 1:
The patent introduces dynamic voltage selection where the control logic voltage domain changes based on the bit significance being processed. During the conversion process, the system dynamically switches between high voltage control for significant bits and low voltage control for less significant bits. This dynamic adaptation optimizes the propagation delay characteristics for each stage of the conversion process, reducing overall conversion time while maintaining operational stability through appropriate voltage selection for each bit position.
Data Source
AI summary
An analog-to-digital converter includes a low voltage power supply rail, a high voltage power supply rail, successive approximation circuit, a level shifter, and a capacitive digital-to-analog converter (CDAC). The successive approximation circuitry is coupled to the low voltage power supply rail. The level shifter is coupled to the high voltage power supply rail and includes inputs coupled to first outputs of the successive approximation circuitry. The CDAC includes a first segment and a second segment. The first segment includes a first plurality of capacitors, and a first plurality of switches coupled to outputs of the level shifter. The second segment includes a second plurality of capacitors, and a second plurality of switches coupled to second outputs of the successive approximation circuitry.