SAR ADC Reference Voltage Switching for Lower Conversion Power

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Solution Overview

Problem

Successive-approximation-register (SAR) analog-to-digital converters (ADCs) consume a significant amount of power during signal conversion.

Innovation Solution

The proposed analog-to-digital converter includes a comparator, control logic, and a reference voltage adjustment circuit with pull-up and pull-down circuits. The control logic outputs control signals based on the comparator's output, and these signals adjust the reference voltages applied to capacitor arrays, optimizing power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If a SAR ADC uses conventional capacitor arrays with fixed reference voltages, then the conversion function is achieved, but power consumption is high

Engineering Contradiction:
Improvepower consumptionVSAvoidcircuit complexity
Core Design Contradiction:
Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The capacitor array is divided into multiple groups, with each group having independently controllable switches that can selectively connect to different reference voltage levels. This segmentation allows only the necessary capacitor groups to be activated during each conversion cycle, reducing overall power consumption while maintaining the conversion function.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The reference voltage connections are made dynamic through control switches that can reconfigure which capacitor groups connect to which reference voltage levels based on the conversion stage. This dynamic reconfiguration enables the circuit to adapt its power consumption to the actual conversion needs, avoiding continuous full-power operation.

Inventive Principle:
Principle #15Dynamics

2Reliability

If reference voltages are continuously applied to all capacitors, then the ADC operation is maintained, but dynamic power consumption increases

Engineering Contradiction:
Improveconversion reliabilityVSAvoiddynamic power loss
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

Reference voltages are applied periodically rather than continuously, synchronized with the conversion phases. During non-active phases, the connection switches disconnect the reference voltages from the capacitor arrays, eliminating dynamic power consumption during these periods while ensuring reference voltages are available when needed for conversion operations.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

Different capacitor groups receive reference voltage connections selectively based on their specific function in the conversion process. Only the capacitor groups currently needed for the conversion operation maintain active reference voltage connections, while others are disconnected, thereby reducing overall dynamic power loss without compromising conversion reliability.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS12224766B2Analog digital converter and method for analog to digital converting in the analog digital converter
Publication Date: 2025.02.11 SAMSUNG ELECTRONICS CO LTD
  • US12224766B2 patent drawing
  • US12224766B2 patent drawing
  • US12224766B2 patent drawing

AI summary

An analog-to-digital converter is provided. An analog-to-digital converter includes a comparator including a first input node receiving an output of a plurality of first unit capacitors and a second input node receiving an output of a plurality of second unit capacitors, a control logic configured to output first and second control signals on the basis of an output signal of the comparator, and a reference voltage adjustment circuit configured to adjust an output voltage provided to the comparator on the basis of the first and second control signals. The reference voltage adjustment circuit comprises a first pull-up circuit configured to apply a first reference voltage to each of the plurality of first unit capacitors and a first pull-down circuit configured to apply a second reference voltage to each of the plurality of second unit capacitors, based on v.