SAR ADC Capacitor Weight Calibration for Better Linearity
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Solution Overview
Problem
Successive approximation analog-to-digital converters (ADCs) are prone to non-linearities due to mismatch in reference elements, leading to differential and integral non-linearities, which cause unwanted spurious tones in AC signal conversions, such as in radar or audio systems.
Innovation Solution
The method involves measuring the weights of DAC reference elements by performing a sampling operation with specific reference voltage configurations across different capacitor arrays, balancing capacitance during sampling to reduce voltage transients and offsets, and using these measurements to correct the ADC output, thereby reducing calibration errors and improving spurious-free dynamic range (SFDR).
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If successive approximation ADCs use simple architecture and low power consumption, then device complexity and energy use are reduced, but non-linearities occur due to mismatch in reference elements
Solution Approach 1:
The patent applies preliminary calibration before normal ADC operation to measure and correct capacitor weight deviations. The calibration process determines actual weights of capacitor arrays and stores correction values, which are then used during conversion to compensate for manufacturing mismatches, thereby achieving high linearity without increasing operational complexity
Solution Approach 2:
The patent changes the operational parameters of the ADC by implementing variable capacitor weighting based on measured deviations. During calibration, actual capacitor weights are measured and stored, and these measured parameters are used to adjust the conversion process, transforming fixed mismatched parameters into adjustable correction factors that improve linearity
2Ease of operation
If successive approximation ADCs use simple architecture and low power consumption, then ease of operation is improved, but spurious tones are generated in AC signal conversions
Solution Approach 1:
The patent performs preliminary calibration to measure actual capacitor weights and generate correction values before AC signal conversion. This pre-measurement and pre-correction approach eliminates spurious tones during normal operation without adding complexity to the conversion process itself, maintaining ease of operation while removing harmful artifacts
Solution Approach 2:
The patent implements a feedback mechanism where measured capacitor weight deviations are used to adjust the conversion process. The calibration system measures actual weights, compares them to ideal values, and feeds back correction information that compensates for mismatches during AC signal conversion, thereby eliminating spurious tones
3Productivity
If calibration measurements are performed without balancing capacitance, then measurement speed is improved, but voltage transients and offsets increase causing measurement errors
Solution Approach 1:
The patent applies preliminary balancing of capacitance connections before performing weight measurements. By pre-configuring the capacitor array to have balanced total capacitance to reference voltages, the system eliminates voltage transients and offsets that would otherwise corrupt measurements, enabling both fast and accurate calibration
Solution Approach 2:
The patent creates equipotential conditions during calibration by balancing the total capacitance connected to each reference voltage. This ensures that no net charge flow or voltage transients occur during measurement, providing stable measurement conditions that achieve high precision without sacrificing measurement speed
Data Source
Figure 1
Figure 2A
Figure 2B~2C
AI summary
In accordance with an embodiment, a method for operating a successive approximation ADC comprising a first capacitor array includes measuring a first weight of an MSB-ath bit of the ADC by applying a first reference voltage to first terminals of capacitors of the first capacitor array corresponding to the MSB-ath bit, applying a second reference voltage to first terminals of capacitors of the first capacitor array corresponding to significant bits lower than the MSB-ath bit, applying the first reference voltage to first terminals of a first set of capacitors of the first capacitor array corresponding to significant bits higher than the MSB-ath bit, and applying the second reference voltage to first terminals of a second set of capacitors of the first capacitor array corresponding to the significant bits higher than the MSB-ath bit; subsequently, a weight of a capacitance of the capacitors corresponding to the MSB-ath bit is successively approximated.