Split-Capacitor SAR ADC Calibration for Parasitic Weighting Errors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The exponential growth in chip area and production cost due to increased accuracy requirements in SAR ADCs is exacerbated by parasitic capacitance, leading to decreased effective bits and increased power consumption.
Innovation Solution
A calibration system for split capacitor arrays in SAR ADCs that reduces weighting errors by using a switchable MSB array and a calibration DAC array with a binary array of unit capacitors and switches, allowing for front-end calibration without additional capacitors, thereby reducing chip area and comparator design complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the number of capacitors in the capacitor array is increased to improve ADC accuracy, then the measurement precision is improved, but the chip area occupied by the capacitor array increases exponentially
Solution Approach 1:
The capacitor array is divided into two separate arrays: a first capacitor array connected to the positive input terminal and a second capacitor array connected to the negative input terminal. This segmentation allows the use of fewer capacitors per array while maintaining the required resolution, thereby reducing the total chip area occupied by the capacitor arrays.
2Area of stationary object
If the split capacitor array is used to reduce chip area, then the area of stationary object is reduced, but the device becomes sensitive to parasitic capacitance causing weighting errors
Solution Approach 1:
A calibration mechanism is implemented that detects weighting errors caused by parasitic capacitance and applies corrective digital values. The calibration process measures the actual weighting of each capacitor and generates correction values that are applied during normal operation, forming a feedback loop that compensates for parasitic effects.
Solution Approach 2:
The system changes the operating parameters by applying different digital correction values to compensate for parasitic capacitance effects. During calibration, specific digital values are applied to characterize the parasitic capacitance, and these characterized parameters are then used to adjust subsequent conversions, effectively changing the system's response to eliminate errors.
3Measurement precision
If calibration is performed to reduce weighting errors, then the measurement precision is improved, but the complexity of the device increases
Solution Approach 1:
The same capacitor arrays and switches used during normal ADC operation are reused during the calibration process. The first and second capacitor arrays, along with their associated switches, serve dual purposes: performing actual conversions during normal operation and characterizing parasitic capacitance during calibration, eliminating the need for separate dedicated calibration hardware.
4Area of stationary object
If the number of capacitors is reduced in split capacitor array, then the chip area is reduced, but power consumption increases due to sensitivity to parasitic capacitance
Solution Approach 1:
The calibration system characterizes parasitic capacitance effects and applies digital correction values to compensate for the increased sensitivity. By correcting the weighting errors through feedback, the system can operate with fewer capacitors at reduced power consumption while maintaining accuracy through the applied corrections.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The system effectively reduces weighting errors to LSB/4, increasing the effective number of bits of the ADC without excessive power consumption or gain requirements, improving SFDR and SNDR by 25.6976 dB and 13.5106 dB, respectively, and ENOB by 2.2442 bits.
Implementation Method 1
a comparator, a P-terminal array, an N-terminal array, and a control logic unit; the comparator has a positive input and a negative input
Implementation Method 2
split capacitance successive approximation analog-to-digital converters; the P-terminal array comprises a least significant bit (LSB) array, a bridge capacitor CBR, and a most significant bit (MSB) array
Data Source
AI summary
The present disclosure relates to the field of microelectronics and solid-state electronics, and in particular to a calibration system and method for weighting errors brought about by parasitic capacitance in split capacitor-based successive approximation analog-to-digital converters. The method uses an MSB array that does not add additional capacitors, only a switch SM to reduce the comparator design difficulty. Meanwhile, an LSB array may add a calibration DAC array CA including a binary array of P-bit unit capacitors, a calibration structure Cfraq, and a ground switch Sk. The calibration structure Cfraq includes four unit capacitors and two switches S1 and S2. By controlling the switches S1 and S2 different capacitance values can be generated to reduce the chip area consumption. This structure can reduce the error to LSB/4 and the weighting error of the ADC, and increases the effective number of bits of the ADC without excessively increasing comparator gain.