SAR ADC Analog Switch Circuit for Wide Sampling Rates
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Solution Overview
Problem
Existing analog-to-digital converters require individual design for each sampling rate, leading to increased cost and inefficiency due to leakage currents in analog switches, limiting their ability to operate across a wide range of sampling rates.
Innovation Solution
A successive approximation register analog-to-digital converter with an analog switch circuit that includes PMOS and NMOS switches, controlled by a digital controller to minimize leakage currents by equalizing voltages across the switches, thereby reducing leakage currents and enabling a wide sampling rate operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If an analog-to-digital converter is designed for a specific sampling rate, then the converter achieves optimal performance for that rate, but the converter cannot operate efficiently across a wide range of sampling rates
Solution Approach 1:
The patent implements a universal analog-to-digital converter design that can operate across multiple sampling rates (100 Ksps to 10 Msps) by using a standardized capacitor array and switch configuration that functions effectively throughout this wide range, eliminating the need for separate designs for different sampling rates
2Speed
If analog switches are used in the capacitor array, then the converter can operate at higher sampling rates, but leakage currents increase which degrades conversion accuracy
Solution Approach 1:
The patent applies equipotentiality by connecting the gate terminal of each analog switch to the same potential as its source terminal during the hold phase, ensuring that no voltage difference exists across the switch channels. This eliminates the driving force for leakage current while maintaining the switch in a controlled state, thereby preserving conversion accuracy at high sampling rates
3Reliability
If individual converter designs are created for each sampling rate requirement, then optimal performance is achieved for each rate, but overall system cost increases
Solution Approach 1:
The patent creates a single universal converter design that can be manufactured once and deployed across multiple applications requiring different sampling rates (from 100 Ksps to 10 Msps), significantly reducing development costs, manufacturing complexity, and inventory requirements compared to producing separate optimized converters for each sampling rate
Data Source
AI summary
An analog switch circuit in a successive approximation register analog-to-digital converter for a wide sampling rate includes a first PMOS switch controlled by a voltage of a second control node, second PMOS switch controlled by a control voltage, a first control switch unit controlling voltages of first and second control nodes, a first NMOS switch controlled by a voltage of a fourth control node, a second NMOS switch controlled by the control voltage und, and a second control switch unit controlling voltages of third and fourth control nodes.