Asynchronous SAR ADC Word Completion for Metastability Control
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Solution Overview
Problem
Conventional analog-to-digital conversion methods are costly, cumbersome, and inefficient, often being complex and time-consuming, which can reduce yields.
Innovation Solution
An asynchronous successive approximation register analog-to-digital converter (SAR ADC) with a word completion function is implemented, utilizing a photonically-enabled integrated circuit that includes optical modulators, photodiodes, and grating couplers, and employs a novel word completion method that simplifies the conversion process by using asynchronous timing and sampling pulses generated by a common clock generator for all SAR ADCs in a bank, eliminating the need for a timer and ensuring accurate bit evaluation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional analog-to-digital conversion methods are used, then conversion accuracy can be achieved, but the system becomes complex and time-consuming
Solution Approach 1:
The patent replaces conventional electronic timing and control mechanisms with a photonically-enabled system using optical modulators, photodiodes, and grating couplers. The optical domain provides inherent timing reference through light pulses, eliminating the need for complex electronic timers and synchronisation circuits while maintaining conversion accuracy.
Solution Approach 2:
The patent introduces an optical intermediary system that mediates between the analog input signal and digital output. Optical pulses serve as an intermediate timing reference that synchronizes the successive approximation process without requiring complex electronic timing logic, thereby reducing system complexity.
2Productivity
If conventional analog-to-digital conversion methods are used, then conversion can be performed, but the process is time-consuming and reduces yields
Solution Approach 1:
The patent employs periodic optical sampling pulses to trigger successive approximation cycles. Each optical pulse initiates a conversion cycle, providing precise periodic timing that accelerates the conversion process. The periodic optical reference enables parallel processing and reduces idle time between conversions, improving productivity.
Solution Approach 2:
The patent uses optical modulators to pre-condition and pre-time the sampling signals before they reach the ADC core. By establishing the timing reference in advance through optical means, the system eliminates setup delays and reduces the overall conversion time, thereby improving yield.
3Adaptability or versatility
If timing references are shared across multiple SAR ADCs, then resource utilization improves, but metastability issues arise
Solution Approach 1:
The patent replaces electronic timing distribution with optical timing references. Optical pulses provide inherent isolation between channels while maintaining synchronization, eliminating the metastability issues that arise from shared electronic timing references. Each SAR ADC receives optically-isolated timing signals that prevent cross-channel interference.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the word completion block of the SAR ADC, reduces metastability issues, and enhances the efficiency of analog-to-digital conversion, improving yield and reducing complexity and cost.
Implementation Method 1
optical modulators, photodiodes, and grating couplers
Implementation Method 2
optical modulators, photodiodes, and grating couplers
Implementation Method 3
optical modulators, photodiodes, and grating couplers
Data Source
AI summary
Methods and systems for an asynchronous successive approximation register analog-to-digital converter with word completion may include a successive approximation register (SAR) analog-to-digital converter (ADC) including a switched capacitor digital-to-analog converter (DAC), a word completion block, a comparator, and a metastability detector. The SAR ADC may sample a received analog electrical signal using the DAC, and convert the electrical signal to an n-bit digital signal by evaluating bits from a most significant bit to a least significant bit using the comparator. If the metastability detector determines that a time to evaluate one of the bits is longer than a threshold time, the metastability detector generates a metastability flag for each such bit. The converting may be initiated using a conversion enable clock pulse generated in the first SAR ADC. The metastability flag may be generated when a conversion enable pulse overlaps with a sampling clock pulse.