Single-Ended SAR DAC Ripple Cancellation Using a Non-Switching DAC
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing SAR ADCs face challenges in mitigating reference voltage ripple, particularly in high-resolution applications, due to large DAC capacitors and parasitic elements, which compromise low power consumption and small form factor advantages.
Innovation Solution
Implementing a non-switching DAC in conjunction with a switching DAC, using previous conversion results to cancel reference voltage ripple by applying previous code to the non-switching DAC during conversion phases, leveraging oversampling to maintain low power consumption and small form factor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If large bypass capacitors are used to mitigate reference voltage ripple, then reference voltage stability is improved, but device area and power consumption increase
Solution Approach 1:
The patent introduces a ripple cancellation DAC as an intermediary component that generates a cancellation signal to counteract reference voltage ripple. This mediator approach avoids the need for large bypass capacitors while achieving reference voltage stability, thus resolving the contradiction between reliability and device area.
Solution Approach 2:
The patent extracts and separately handles the reference voltage ripple component by using the ripple cancellation DAC to generate an opposing signal. By isolating and canceling the ripple component rather than suppressing it with large capacitors, the solution maintains reference voltage stability without increasing device area.
2Reliability
If large bypass capacitors are used to mitigate reference voltage ripple, then reference voltage stability is improved, but power consumption increases
Solution Approach 1:
The ripple cancellation DAC acts as a mediator that actively counteracts reference voltage ripple through signal cancellation rather than passive suppression. This active cancellation mechanism achieves reference voltage stability with lower power consumption compared to large bypass capacitors.
Solution Approach 2:
The patent employs feedback mechanisms where the ripple cancellation DAC continuously monitors and counteracts reference voltage ripple. This feedback-based active cancellation achieves stable reference voltage with reduced power consumption compared to passive capacitor-based suppression.
3Use of energy by stationary object
If DAC redundancy techniques are used to allow higher ripple, then power consumption is reduced, but measurement precision deteriorates
Solution Approach 1:
The ripple cancellation DAC serves as a mediator that enables the system to maintain low power consumption while preserving measurement precision. By actively canceling reference voltage ripple, it allows the ADC to operate with standard DAC configurations rather than requiring redundant DACs, thus maintaining conversion accuracy at lower power consumption.
Solution Approach 2:
The patent converts the harmful effect of reference voltage ripple into a beneficial cancellation signal. By generating an opposing ripple signal through the ripple cancellation DAC, the system eliminates the harmful ripple effect while maintaining low power consumption and standard DAC configurations, thereby preserving measurement precision.
4Measurement precision
If large DAC capacitors are used in high-resolution ADCs, then conversion accuracy is improved, but device area increases
Solution Approach 1:
The ripple cancellation DAC acts as a mediator that enables high-resolution conversion accuracy without requiring excessively large DAC capacitors. By canceling reference voltage ripple that would otherwise require large capacitors for suppression, the system achieves high conversion accuracy with compact capacitor sizes, thus resolving the area-accuracy tradeoff.
Data Source
AI summary
A method for reference ripple cancellation in an oversampled single-ended Successive Approximation Register (SAR) Analog to Digital Converter (ADC) includes sampling an input voltage onto a plurality of first capacitors of a switching Digital to Analog Converter (DAC) during a sampling phase. A first output of the switching DAC is compared to a second output of a non-switching DAC during a first conversion phase. A first digital code is generated from the comparison of the first output to the second output. The first digital code is applied to the non-switching DAC during a second conversion phase subsequent to the first conversion phase.


