Hybrid SAR-Delta-Sigma ADC Feedback for Stable High Resolution
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Solution Overview
Problem
Existing semiconductor devices that convert analog signals to digital signals face challenges in reducing power consumption while maintaining high resolution and operational stability, particularly due to vulnerabilities in coefficient errors and physical noise issues in coarse-fine ADC architectures.
Innovation Solution
The semiconductor device employs a multi-bit Successive Approximation Register (SAR) ADC as a coarse converter and a delta-sigma modulator as a fine converter, with a loop filter and digital-to-analog converter (DAC) to generate a feedback signal, and includes a gain block, integrators, and filters to improve noise shaping and stability, avoiding the need for error compensation circuits and reducing voltage variation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a coarse-fine ADC architecture is used to achieve high resolution, then measurement precision is improved, but power consumption increases and operational stability deteriorates due to coefficient errors and physical noise
Solution Approach 1:
The patent divides the ADC into a coarse converter (first ADC) and a fine converter (delta-sigma modulator), where each segment performs a specific function. The coarse converter handles the majority of the conversion with lower power consumption, while the fine converter refines the result with higher precision, achieving high resolution without proportionally increasing power consumption.
Solution Approach 2:
The patent introduces a loop filter as an intermediary component between the coarse and fine converters. This loop filter compensates for coefficient errors and reduces physical noise, improving operational stability without requiring additional high-power compensation circuits in the main conversion path.
2Measurement precision
If a coarse-fine ADC architecture is used to achieve high resolution, then measurement precision is improved, but operational stability deteriorates due to coefficient errors and physical noise
Solution Approach 1:
The loop filter serves as an intermediary that stabilizes the system by compensating for coefficient errors and filtering physical noise. It processes the output from the coarse converter before it enters the fine converter, preventing error propagation and maintaining operational stability throughout the conversion process.
Solution Approach 2:
The patent implements a feedback mechanism where the output of the delta-sigma modulator is fed back through the loop filter to correct errors in the coarse converter output. This feedback loop continuously adjusts for coefficient errors and noise, improving operational stability while maintaining high resolution.
3Reliability
If error compensation circuits are added to improve operational stability, then reliability is improved, but device complexity increases
Solution Approach 1:
The loop filter is positioned as an intermediary component that handles error compensation in a streamlined manner. Rather than adding complex compensation circuits throughout the system, the loop filter centralizes the error correction function, maintaining reliability while minimizing additional complexity.
Solution Approach 2:
The loop filter performs multiple functions simultaneously: it filters noise, compensates for coefficient errors, and shapes the signal for the fine converter. This multi-functionality reduces the need for separate dedicated compensation circuits, thereby limiting the increase in device complexity while improving operational stability.
Data Source
AI summary
A semiconductor device includes; a loop filter that receives a differential analog signal and generates a residue signal indicating an error between an analog input signal and an feedback signal, a first ADC that receives the residue signal and generates a first digital representation, a second ADC that receives the analog input signal and generates a second digital representation corresponding to the analog input signal, and a digital to analog converter (DAC) that receives a sum of the first digital representation and the second digital representation and generates the analog feedback signal. At least the first ADC is a multi-bit Successive Approximation Register ADC.