SAR Duty Cycle Correction Circuit for Fast Clock Tracking
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Solution Overview
Problem
Existing duty cycle correction circuits in synchronous semiconductor memory devices, such as DDR SDRAM, face limitations in speed due to charge pump speed limitations and lack of frequency variation tracking, leading to long correction times and inadequate performance across a wide range of input frequencies.
Innovation Solution
A duty cycle correction circuit comprising a duty cycle detector, filter, comparator, SAR DAC, equalization device, pass gate circuit, and duty cycle corrector, which generates internal clock signals with a corrected duty cycle by using a SAR algorithm and voltage equalization to improve correction speed and frequency adaptability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a charge pump is used to generate control signals for duty cycle correction, then the circuit can correct the duty cycle of external clock signals, but the charge pump speed limitation results in long duty cycle correction time
Solution Approach 1:
The patent replaces the charge pump mechanism with a capacitor-based voltage generation system. Instead of using a charge pump to generate control signals DCC and DCCB, the invention uses capacitors C1 and C2 to store and provide voltages, controlled by switch arrays (SW1-SW4, SW5-SW8) that are driven by bit-weighted control signals (B7-B0). This substitution eliminates the speed limitation of charge pumps while maintaining the ability to generate precise duty cycle correction signals.
2Stability of the object's composition
If a fixed duty cycle correction circuit is designed, then it can provide stable correction, but it lacks the means of tracking frequency variation of input clock signal, limiting operation to narrow frequency range
Solution Approach 1:
The patent introduces dynamic adaptability through a frequency detection circuit that monitors the input clock signal frequency and generates corresponding control signals. The system includes adjustable capacitor arrays (C1-C4, C5-C8) with switch arrays that can be reconfigured based on detected frequency conditions. This allows the duty cycle correction circuit to dynamically adjust its parameters to track frequency variations while maintaining stable correction performance across different operating conditions.
Solution Approach 2:
The patent implements a feedback mechanism where the frequency detection circuit continuously monitors the input clock signal and provides feedback to adjust the capacitor configuration and control signals. This closed-loop approach enables the circuit to automatically adapt to frequency variations, ensuring both stability of correction and versatility across wide frequency ranges.
3Productivity
If multiple control signals and switches are added to improve correction speed and frequency tracking, then performance improves, but the device complexity increases
Solution Approach 1:
The patent segments the duty cycle correction function into multiple independent components: frequency detection circuit, capacitor arrays (C1-C4, C5-C8), switch arrays (SW1-SW4, SW5-SW8), and control logic units. Each segment performs a specific function and can be independently optimized or adjusted. This modular segmentation enables improved correction speed and frequency tracking while managing complexity through functional decomposition.
Solution Approach 2:
The patent utilizes parameter changes by employing bit-weighted control signals (B7-B0) that can independently adjust the configuration of capacitor arrays and switch arrays. This allows dynamic adjustment of circuit parameters (capacitance values, switch states) to optimize correction speed and frequency response without permanently increasing structural complexity, as the same physical components can be reconfigured for different operating conditions.
Data Source
AI summary
A duty cycle correction circuit comprises a duty cycle detector, a filter, a comparator, a SAR DAC, an equalization device, a pass gate circuit, and a duty cycle corrector. The duty cycle detector generates control signals in response to internal clock signals. The equalization device equalizes voltage levels of the control signals, and the pass gate circuit applies the control signals to the duty cycle corrector. The filter obtains average voltages of the control signals. The comparator compares output signals from the filter to generate a comparison result. The SAR DAC performs a SAR algorithm to generate analog output signals based on the comparison result. The duty cycle corrector receives external clock signals, the analog output signals, and output signals from the pass gate circuit to generate the internal clock signals with a corrected duty cycle.