SAR-Feedback ADC Architecture Without Multi-Bit DAC Nonlinearity
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Solution Overview
Problem
Conventional analog-to-digital converters (ADCs) and cascaded ADCs like sigma-delta modulators suffer from nonlinear errors and increased power consumption due to the use of multi-bit digital-to-analog converters (DACs), which require complex circuitry and dynamic element matching to compensate for mismatches.
Innovation Solution
The use of a successive approximation register (SAR) quantizer in the feedback loop of the ADCs, which generates a quantization error signal instead of the quantizer output, eliminates the need for a multi-bit DAC, thereby reducing nonlinear errors and power consumption by reusing the SAR DAC for feedback connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a multi-bit DAC is used in the feedback loop of a sigma-delta modulator, then the ADC can achieve wide range applications and functional requirements, but nonlinear errors and signal distortions occur due to mismatch within the DAC elements
Solution Approach 1:
The patent extracts the problematic multi-bit DAC from the feedback loop by using a 1-bit DAC instead. The quantization error signal is directly fed back through this simplified 1-bit DAC, eliminating the mismatch issues inherent in multi-bit DAC elements while maintaining the necessary feedback functionality for sigma-delta modulation.
Solution Approach 2:
The patent changes the bit parameter of the DAC from multi-bit to 1-bit. This parameter change fundamentally alters the feedback mechanism, converting it from a direct multi-bit digital-to-analog conversion to a quantization error feedback approach that inherently avoids the nonlinearity problems of multi-bit DACs.
2Measurement precision
If a multi-bit DAC is used for quantization error feedback in cascaded ADCs, then the conversion precision can be maintained, but extra circuitry is required and power consumption increases
Solution Approach 1:
The patent removes the need for separate multi-bit DACs in each stage of the cascaded ADC by implementing a 1-bit DAC architecture. The quantization error from each stage is directly fed back through simple 1-bit DACs, eliminating the complex multi-bit conversion circuitry while preserving the precision benefits of cascaded noise shaping.
Solution Approach 2:
The SAR quantizer's internal DAC is reused to generate the quantization error feedback signal, making the system self-sufficient. This eliminates the need for additional dedicated DACs in the feedback paths, reducing overall circuit complexity while maintaining the precision required for high-resolution conversion.
3Adaptability or versatility
If a multi-bit DAC is used in the ADC feedback loop, then the functional requirements can be met, but power consumption increases due to the complex circuitry
Solution Approach 1:
The patent extracts the high power consumption element (multi-bit DAC) from the system by replacing it with a 1-bit DAC architecture. The quantization error feedback mechanism achieves the same functional goals with dramatically reduced power consumption, as 1-bit DACs require significantly fewer active elements and less switching activity.
Solution Approach 2:
The patent employs simple 1-bit DACs that are essentially disposable in terms of complexity - they require minimal circuit elements and can be implemented with simple switches and capacitors. These simple feedback DACs perform their function efficiently without the ongoing power burden of complex multi-bit DACs.
Data Source
AI summary
The invention relates to an analog-to-digital converter (ADC), configured to convert an analog input signal to a digital output signal, the ADC comprising: an integrator configured to generate an integrated signal based on the analog input signal and subtrahend signals; and a quantizer configured to: receive the integrated signal from the integrator, generate the digital output signal; and generate a quantization error signal, wherein the ADC is further configured to, in a feedback loop: provide the integrated signal and the quantization error signal as the subtrahend signals to the integrator.