SAR Sample-and-Hold Circuit for Droop-Free Signal Regeneration
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Solution Overview
Problem
Sample and hold circuits in analog-to-digital converters face challenges in maintaining accurate representation of analog signals due to droop effects during the conversion process, which affect the precision of digital signal regeneration and equivalent analog voltage generation.
Innovation Solution
A successive approximation register (SAR) analog-to-digital converter (ADC) with a capacitive digital-to-analog converter (CDAC) and a comparator that samples an analog input signal, stores it digitally, and then regenerates the signal to recharge capacitors, with the comparator configured as an amplifier to generate an equivalent analog voltage by feeding its output back to its inverting input.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the comparator operates in comparison mode during sampling and conversion, then the analog input signal can be accurately converted to digital signal, but droop effects occur during the conversion process that affect precision
Solution Approach 1:
The comparator dynamically switches between two operational modes: comparison mode during sampling/conversion and amplifier mode during signal regeneration. This dynamic reconfiguration allows the system to optimize for different functional requirements at different times, eliminating droop effects while maintaining conversion accuracy.
Solution Approach 2:
The system changes the operating parameters of the comparator by switching its feedback configuration. During sampling and conversion, the comparator operates in open-loop comparison mode. During signal regeneration, the output is fed back to the inverting input, transforming the comparator into a high-gain amplifier mode, thereby changing its electrical characteristics to suit the current operational phase.
2Measurement precision
If the comparator output is fed back to the inverting input to operate as an amplifier, then equivalent analog voltage generation precision is improved, but the circuit complexity increases
Solution Approach 1:
The comparator serves multiple functions within the same circuit architecture. It performs both comparison operations during ADC conversion and amplification during signal regeneration, eliminating the need for separate comparator and amplifier circuits. This multi-functionality reduces overall system complexity while achieving high precision analog voltage generation.
Solution Approach 2:
The system employs feedback by connecting the comparator output to its inverting input during the regeneration phase. This feedback mechanism transforms the comparator into a high-gain amplifier, enabling precise analog voltage generation from the digitally stored signal without requiring additional complex circuitry.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the precision of digital signal conversion and regeneration, reducing droop effects and improving the accuracy of the equivalent analog voltage generation, thereby maintaining the integrity of the sampled analog signal.
Implementation Method 1
A comparator, which is coupled to the CDAC, converts the sampled analog input signal into a digital signal
Implementation Method 2
a capacitive digital to analog converter (CDAC) that further includes a plurality of capacitors to sample an analog input signal
Implementation Method 3
the comparator is configured as an amplifier to generate an equivalent analog voltage of the stored digital signal
Data Source
AI summary
A device includes a capacitive digital to analog converter (CDAC) that further includes a plurality of capacitors to sample an analog input signal. The sampled analog input signal is converted into a digital signal and the digital signal is stored by a successive approximation register (SAR). Thereafter, the SAR regenerates the stored digital signal to a reset plurality of capacitors, and a comparator is configured as an amplifier to generate an equivalent analog voltage of the stored digital signal.