SAR Time-to-Digital Converter With Time Difference Amplifier Gains
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Solution Overview
Problem
Successive approximation register (SAR)-based analog-to-digital converters (ADCs) face challenges in area consumption, power usage, and matching requirements due to the need for large capacitor arrays and complex finite state machines, particularly in high-resolution applications where binary weighting elements are critical for phase difference measurements.
Innovation Solution
The implementation of a SAR-based time-to-digital converter circuit using a time difference amplifier (TDA) with programmable binary weighted gains, eliminating the need for capacitor arrays and complex finite state machines by employing digital switches and time latches for binary weighting, allowing for efficient area and power usage while maintaining performance metrics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If binary weighted capacitor arrays are used in SAR-based ADCs for high-resolution phase difference measurements, then measurement precision is improved, but area consumption increases significantly
Solution Approach 1:
The patent replaces the traditional capacitor-based binary weighted DAC with a time-mode signal processing system. Instead of using physical capacitor arrays to achieve binary weighting, the invention uses time latches and delay elements to perform binary search operations in the time domain. This substitution eliminates the need for large capacitor arrays while maintaining the SAR algorithm's functionality for high-resolution phase difference measurements.
Solution Approach 2:
The patent transforms the conversion domain from voltage mode to time mode. By changing the operating parameter from voltage to time, the system achieves binary weighting through temporal relationships rather than physical capacitor values. The time difference amplifier and time latches manipulate time intervals to perform the binary search, fundamentally changing how the SAR algorithm operates and eliminating area-consuming capacitor structures.
2Measurement precision
If large capacitor arrays are implemented for binary weighting in SAR-based converters, then conversion accuracy is improved, but power consumption increases
Solution Approach 1:
The patent replaces the energy-intensive capacitor charging/discharging operations with time-mode signal processing. The time latches and delay elements consume significantly less power than large capacitor arrays, especially during the binary search operations. The time difference amplifier operates with low power consumption while achieving the same binary weighting function that previously required high-power capacitor switching.
Solution Approach 2:
By transitioning from voltage mode to time mode operation, the patent eliminates the continuous power consumption associated with maintaining large capacitor arrays. The time-based implementation uses transient signal processing rather than sustained voltage levels, dramatically reducing static and dynamic power consumption while preserving conversion accuracy.
3Measurement precision
If capacitor-based binary weighting is used in SAR converters, then conversion precision is improved, but device complexity increases due to matching requirements and switch design
Solution Approach 1:
The patent replaces the complex capacitor matching and switch design requirements with simpler time-mode circuitry. Instead of precisely matching capacitor values and designing switches with different drive capabilities, the invention uses identical time latches and delay elements that are inherently matched by their identical structure. The time difference amplifier and time latches provide the necessary binary weighting without requiring component matching or complex switch designs.
Solution Approach 2:
The transition to time-mode operation eliminates the need for precise component matching. In the time domain, binary weighting is achieved through the number of delay stages and latch configurations rather than through precisely matched capacitor values. This parameter change from voltage to time domain fundamentally simplifies the circuit design while maintaining high conversion precision.
4Adaptability or versatility
If traditional voltage-mode SAR ADC architecture is used, then conversion functionality is achieved, but adaptability to low voltage and advanced technology nodes is limited
Solution Approach 1:
The patent fundamentally changes the operating domain from voltage mode to time mode, enabling the converter to operate effectively at low supply voltages. Time-mode signal processing is inherently more suitable for low-voltage operation because it relies on temporal relationships and signal edges rather than voltage levels. This parameter change allows the SAR-based converter to maintain high measurement precision while being highly adaptable to low voltage modes and advanced technology nodes.
Solution Approach 2:
By replacing voltage-mode circuitry with time-mode circuitry, the patent achieves better adaptability to modern low-voltage and high-frequency technology nodes. The time latches, delay elements, and time difference amplifier are naturally suited for operation at lower voltages and higher frequencies, providing both voltage scaling capability and maintained conversion performance.
Data Source
AI summary
A successive approximation register based time-to-digital converter circuit with a time difference amplifier (TDA). A first TDA which applies a gain value to a time difference between a first signal edge and a first delayed signal edge to generate a first amplified time difference signal, which is feedback to the first TDA, a second TDA which applies a gain value to a time difference between a second signal edge and a second delayed signal edge to generate a second amplified time difference signal, which is feedback to the second TDA, and a finite state machine which sets another gain value, for a next step in a N step conversion until N steps are completed, in the first and the second TDAs based on a bit value from a previous step, wherein the bit value indicates, for a step, whether the first or second amplified time difference signal is ahead.