SARLock Logic Circuit SAT Attack Resistance
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Solution Overview
Problem
Existing logic locking methods are vulnerable to SAT attacks, which can recover secret keys within a few hours by using Boolean satisfiability procedures, exploiting weaknesses in combinational logic locking procedures and failing to account for the discriminating ability of individual input patterns.
Innovation Solution
The implementation of a SAT attack-resistant logic locking circuit (SARLock) that includes a logic cone, comparator, and XOR gate, where the comparator flips input signals based on distinguishing input patterns and key values, and a masking unit prevents incorrect key combinations from asserting flipped signals, limiting the discriminating ability to a predetermined number of incorrect keys.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional logic locking methods are used, then the implementation is simple with minimal overhead, but the security is weak and vulnerable to SAT attacks that can recover keys within hours
Solution Approach 1:
The logic locking circuit is segmented into multiple independent components: logic cones with key gates, comparators for DIP generation, masking units for output protection, and scrambling units for key obfuscation. Each segment performs a specific security function, making the overall system more resistant to SAT attacks while maintaining modular complexity
Solution Approach 2:
Comparators and masking units are introduced as intermediary components between the key gates and the output. These intermediaries generate distinguishing input patterns and mask outputs based on DIPs, preventing direct SAT attack on the key gates while adding controlled complexity to the circuit architecture
2Reliability
If the number of key gates is increased to improve security, then the resistance to SAT attacks increases, but the area overhead and circuit complexity increase
Solution Approach 1:
Security measures are applied locally at critical logic cones rather than uniformly across the entire circuit. Each logic cone with key gates has its own comparator and masking unit, allowing selective protection of high-value IP while minimizing overall area overhead
Solution Approach 2:
The security strength is controlled by changing parameters such as the number of key gates per logic cone, the complexity of comparators, and the masking depth. This allows flexible adjustment of security level versus area overhead based on specific application requirements
3Loss of time
If multiple distinguishing input patterns are used to increase SAT attack iterations, then the key recovery time increases exponentially, but the discrimination ability against incorrect keys must be carefully controlled
Solution Approach 1:
Comparators pre-compute distinguishing input patterns based on key gate outputs before SAT attack execution. This preliminary action ensures that multiple DIPs are generated with controlled discrimination ability, forcing attackers through exponentially more iterations while maintaining manageable control complexity through systematic DIP generation
Data Source
AI summary
Exemplary embodiment of the present disclosure can include, for example, a logic-locking circuit (“SARLock”), which can include a logic cone(s) receiving a distinguishing input pattern(s) (DIP), a comparator(s) receiving the DIP(s) and a key value(s), and a logic gate(s) connected to an output of the logic cone and to an output of the comparator. A mask(s) can be connected to the comparator(s) and the logic gate(s). The logic gate(s) can be a XOR gate(s). The comparator(s) can be configured to flip a signal(s) based on a combination of the DIP(s) and the key value(s). A mask(s) can be connected to the comparator(s) and the logic gate(s), which can be configured to prevent the flipped signal(s) from being asserted for a correct key value(s).