Self-Aligned Reverse Patterning for Dense Semiconductor Features
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Solution Overview
Problem
The patterning process for forming integrated circuit features on semiconductor substrates is challenging, especially for dense patterns, due to the complexity and difficulty in achieving accurate and efficient transfer of design patterns, which hinders advanced semiconductor technology development.
Innovation Solution
A method involving self-aligned reverse patterning (SARP) processes is used, where a hard mask layer and multiple material layers are patterned and etched to form spacer patterns, allowing for the transfer of dense patterns with improved manufacturability by using these patterns as etching masks to expose and remove specific layers, ultimately forming a patterned hard mask layer for further etching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional photolithography-etching process is used, then the design patterns can be transferred to the semiconductor substrate, but the manufacturing precision and ease of manufacture deteriorate when forming dense patterns due to process complexity
Solution Approach 1:
The patent segments the patterning process into multiple distinct stages: forming first and second material layers with different patterns, performing separate self-aligned reverse patterning (SARP) processes on each layer, and selectively removing portions. This segmentation allows complex dense patterns to be formed through sequential simpler steps, improving both precision and manufacturability compared to attempting to form all patterns in a single conventional photolithography-etching process.
Solution Approach 2:
The patent introduces vertical dimensionality by forming three-dimensional spacer patterns through self-aligned reverse patterning, where spacers are formed on sidewalls of patterns in the first and second material layers at different heights. This vertical stacking enables complex two-dimensional dense patterns to be formed through controlled vertical overlap and selective removal, transforming a planar patterning challenge into a multi-layered solution that improves precision while maintaining manufacturability.
2Productivity
If the dimensions of integrated circuits are shrunk to achieve higher degree of integration, then device performance improves, but the patterning process difficulty increases
Solution Approach 1:
The patent divides the patterning process into segmented stages with distinct functions: first material layer patterning for initial pattern formation, second material layer patterning for additional pattern elements, and selective removal for final pattern definition. This segmentation reduces the complexity of each individual step while achieving high degree of integration through cumulative effect, making the overall process more manageable despite shrinking dimensions.
Solution Approach 2:
The patent introduces spacer patterns as intermediary structures that mediate between the patterns in the first and second material layers. These spacers act as intermediate pattern elements that can be selectively retained or removed to achieve the final dense pattern configuration, providing a bridging mechanism that simplifies the transition from initial pattern formation to final high-density pattern while managing process complexity.
3Adaptability or versatility
If multiple types of dense patterns are incorporated in integrated circuits, then functionality improves, but the patterning process becomes more challenging
Solution Approach 1:
The patent assigns different pattern types to different material layers and processing stages: first material layer patterns and their corresponding spacers form one set of dense patterns, while second material layer patterns and their spacers form another set. This segmentation allows multiple types of dense patterns to be formed through standardized repeated processes applied to different layers, achieving pattern diversity without proportionally increasing overall process complexity.
Solution Approach 2:
The patent employs the same self-aligned reverse patterning process and spacer formation methodology for both the first and second material layers, making the patterning approach universal and multi-functional. This universal process can generate different types of dense patterns depending on the specific pattern definitions in each material layer, achieving versatility in pattern type while maintaining process simplicity and reducing overall complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method simplifies the process steps and enhances manufacturability by enabling the formation of dense patterns on semiconductor substrates, improving the accuracy and efficiency of pattern transfer, particularly for advanced semiconductor technologies.
Implementation Method 1
a first spacer material layer is formed on the array patterns and the first covering layer in a blanket manner
Implementation Method 2
a first spacer material layer is formed on the array patterns and the first covering layer in a blanket manner
Implementation Method 3
etching the first spacer material layer to form first spacer patterns on sidewalls of the first array patterns
Data Source
AI summary
A patterning method is disclosed. A substrate having a hard mask layer and a first material layer formed thereon is provided. The first material layer is patterned into first array patterns and first peripheral patterns. The first array patterns are further transferred into first spacer patterns. Subsequently, a planarization layer and a second material layer are successively formed on the substrate. The second material layer is patterned into second array patterns and second peripheral patterns. The second array patterns are further transferred into second spacer patterns. The second spacer patterns partially overlap the first spacer patterns. The second peripheral patterns do not overlap the first peripheral pattern. The first spacer patterns not overlapped by the second spacer patterns are removed to obtain third array patterns. The hard mask layer is then etched using the third array patterns, the second peripheral patterns and the first peripheral patterns as an etching mask.