SAS Packet-Mode Descrambler Resynchronization After PACKET_SYNC Loss

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Solution Overview

Problem

In SAS Gen5 devices, the loss of synchronization between scramblers and descramblers in packet mode can lead to continuous reception errors due to the timing differences in initializing these components, especially when PACKET_SYNC is missed, causing CRC errors in frames transmitted between initiators and targets.

Innovation Solution

The implementation of a method where the descrambler in the receiver device synchronizes with the scrambler using a specific field in the received frame, utilizing a defined value field and its corresponding expectation value to correctly descramble frames, even in cases of synchronization loss, by calculating the LFSR state and scrambling data to restore synchronization.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the descrambler is initialized on reception of PACKET_SYNC in packet mode, then synchronization between scrambler and descrambler is established, but if PACKET_SYNC is missed due to unexpected operation, the loss of synchronization continues until PACKET_SYNC is exchanged again, causing CRC errors in frames

Engineering Contradiction:
Improvesynchronization reliabilityVSAvoidCRC errors
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent applies preliminary action by calculating and storing the expected value of the defined value field before actual frame reception. When a frame is received, the system retrieves the pre-calculated expected value and compares it with the descrambled defined value field, enabling immediate detection of synchronization loss without waiting for PACKET_SYNC. This preliminary preparation allows the system to proactively handle synchronization issues.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback by continuously comparing the descrambled defined value field with its pre-calculated expected value. When a mismatch is detected, the system generates feedback indicating synchronization loss and triggers re-initialization of the descrambler. This closed-loop feedback mechanism ensures that synchronization status is continuously monitored and corrected, preventing cumulative CRC errors.

Inventive Principle:
Principle #23Feedback

2Ease of operation

If the scrambler is initialized on transmission of PACKET_SYNC and descrambler on reception of PACKET_SYNC, then timing synchronization is achieved in packet mode, but synchronization loss can occur when PACKET_SYNC exchange timing is not aligned with frame exchange timing

Engineering Contradiction:
Improvepacket mode operationVSAvoidsynchronization stability
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The patent uses feedback by comparing the descrambled defined value field with its pre-calculated expected value to detect synchronization status. This continuous monitoring provides feedback on whether the descrambler remains synchronized with the scrambler, enabling the system to detect and correct synchronization drift that occurs when PACKET_SYNC timing is misaligned with frame exchange timing.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent introduces an intermediary mechanism - the defined value field comparison - that acts as a mediator between the scrambler/descrambler synchronization process and the frame data transmission. This intermediary comparison provides an additional layer of verification that bridges the timing gap between PACKET_SYNC initialization and actual frame exchange, ensuring synchronization stability.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If continuous monitoring of synchronization is performed using defined value field comparison, then synchronization loss can be detected early, but additional processing steps are required to calculate and compare expected values

Engineering Contradiction:
Improvesynchronization detection accuracyVSAvoidprocessing complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent reduces processing complexity during frame reception by performing the computationally intensive expected value calculation in advance, before frame transmission begins. This preliminary calculation stores the reference value that can be quickly compared during reception, transforming a complex real-time calculation into a simple retrieval and comparison operation, thus maintaining high reliability without excessive processing burden.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system uses its own pre-calculated expected value as the reference for comparison, making the synchronization detection self-contained. The defined value field in the received frame serves as the test subject, while the pre-calculated expected value acts as the reference standard, allowing the system to self-verify synchronization status without requiring external reference signals or complex external coordination.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS10922054B2Apparatus and method
Publication Date: 2021.02.16 KIOXIA CORP
  • US10922054B2 patent drawing
  • US10922054B2 patent drawing
  • US10922054B2 patent drawing

AI summary

According to one embodiment, an apparatus is capable of exchanging a frame with an external apparatus in a packet mode of a serial attached small computer system interface (SAS). The external apparatus includes a scrambler. The apparatus includes a descrambler and a controller. The descrambler is configured to descramble frame data scrambled by the scrambler. The controller is configured to, in a case where first frame data is received from the external apparatus, synchronize the descrambler with the scrambler using the first frame data and a first value that is to be scrambled by the scrambler to obtain the first frame data.