SASI Structure for GAA Nanosheet FET Leakage Isolation
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Solution Overview
Problem
Current techniques for controlling off-state leakage in gate-all-around (GAA) field effect transistors (FETs) face challenges due to excessive recessing of source-drain regions into the substrate, leading to increased leakage current and degradation of device performance, while conventional punch-through stoppers are sensitive to sub-sheet leakage, especially at short gate lengths, and the presence of a dielectric layer hinders proper epitaxy growth and strain engineering.
Innovation Solution
The implementation of a self-aligned substrate isolation (SASI) layer between the substrate and the gate structure, which acts as an etch stop and reduces gate-to-substrate capacitance, allowing for optimal fin recess control, exposed substrate for epitaxy nucleation, and strain engineering, while minimizing leakage by disconnecting the source-drain regions from the substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If source-drain regions are recessed deeper into the substrate to improve device isolation, then off-state leakage is reduced, but leakage current increases non-linearly and device performance degrades
Solution Approach 1:
A dielectric layer is introduced as an intermediary between the source-drain regions and the substrate. This intermediate layer prevents direct contact and electrical interaction between the conductive source-drain regions and the substrate, thereby blocking the parasitic leakage path while allowing the source-drain regions to maintain their optimal recess depth for device isolation.
2Reliability
If a continuous dielectric layer is formed under the device to isolate source-drain and channel regions from the substrate, then off-state leakage is controlled, but epitaxy growth and strain engineering are hindered
Solution Approach 1:
The dielectric layer is applied selectively only in the source-drain regions where isolation from the substrate is required, while leaving the channel region substrate exposed. This localized approach provides the necessary electrical isolation in the source-drain areas without interfering with epitaxy growth and strain engineering processes in the channel region.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces leakage current, enhances epitaxy growth, and improves strain engineering, leading to better device performance and reduced parasitic leakage, even at short gate lengths, without degrading on-state current.
Implementation Method 1
a self-aligned substrate isolation (SASI) layer located between the substrate and the gate structure and extending over a width of the gate structure
Implementation Method 2
acts as an etch stop and reduces gate-to-substrate capacitance
Implementation Method 3
allowing for optimal fin recess control, exposed substrate for epitaxy nucleation
Data Source
AI summary
A semiconductor structure includes a substrate and a gate-all-around field effect transistor disposed over the substrate. The gate-all-around field effect transistor includes a first source-drain region; a second source-drain region; at least one channel region interconnecting the first and second source drain regions; and a gate structure surrounding the at least one channel region. A self-aligned substrate isolation (SASI) layer is located between the substrate and the gate structure and extends over a width of the gate structure.