SAT-Based ATPG for Multi-Fault Test Pattern Generation
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Solution Overview
Problem
Traditional automatic test pattern generation (ATPG) systems face challenges in generating compact test patterns that effectively detect multiple faults in complex integrated circuit designs, often failing to identify faults simultaneously due to their reliance on input assignments as constraints, which limits fault coverage and increases computational intensity.
Innovation Solution
The implementation of SAT-based ATPG methods that construct a SAT instance from circuit design information and target faults, incorporating a cost function to maximize fault detection, using a SAT solving engine to derive test patterns that detect a maximum number of faults, and iteratively refining the process to remove detected faults, allowing for the generation of test patterns targeting multiple faults.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional structural ATPG methods are used to generate test patterns, then the test generation process is straightforward and uses standard algorithms, but the fault coverage is insufficient for hard-to-detect faults in complex circuits
Solution Approach 1:
The patent replaces traditional structural ATPG methods with SAT-based methods. Instead of using structural analysis and search algorithms like D-algorithm and FAN, the invention transforms the test generation problem into a Boolean satisfiability problem, substituting the mechanical search process with a logical satisfaction check that can more effectively handle complex circuit designs and hard-to-detect faults.
Solution Approach 2:
The patent changes the fundamental parameter representation from structural circuit descriptions to Boolean formulas in CNF form. By transforming the test generation problem into a SAT instance with Boolean variables and clauses, the method enables different solving strategies that can achieve higher fault coverage for complex circuits while managing computational complexity through efficient SAT solving techniques.
2Productivity
If traditional SAT solvers based on DPLL backtrack search are used, then the search process is systematic, but the computational intensity increases and test pattern sets become larger
Solution Approach 1:
The patent applies preliminary action by performing test compaction during the test generation process itself rather than as a separate post-processing step. The SAT-based method generates test patterns with built-in compaction, eliminating the need for subsequent reverse order fault simulation and merging operations, thereby reducing overall computational intensity and improving efficiency.
Solution Approach 2:
The patent inverts the traditional approach by using SAT solving to directly find compact test patterns that satisfy multiple fault detection requirements simultaneously, rather than generating large test sets and then compacting them. This inversion of the generation-then-compaction paradigm into direct compact generation reduces computational energy consumption and improves productivity.
3Reliability
If traditional test compaction techniques use input assignments as constraints, then the compaction process is simplified, but minimal test sets cannot be found and fault coverage is limited
Solution Approach 1:
The patent applies dynamics by making the test pattern generation and compaction process adaptive and iterative. The SAT solver dynamically adjusts test patterns to maximize fault detection, and the process iteratively refines patterns until optimal compaction is achieved. This dynamic approach allows the system to find minimal test sets that achieve complete fault coverage, unlike static traditional methods.
Solution Approach 2:
The patent achieves universality by creating a unified SAT-based framework that simultaneously handles test generation, test compaction, and fault coverage optimization. The same SAT solving mechanism performs multiple functions that traditionally required separate algorithms, enabling the system to find minimal test sets with complete fault coverage while managing complexity through a single integrated approach.
Data Source
AI summary
Disclosed are representative examples of methods, apparatus, and systems for generating test patterns targeting multiple faults using Boolean Satisfiability (SAT)-based test pattern generation methods. A SAT instance is constructed based on the circuit design information and a set of faults being targeted. A SAT solving engine is applied to the SAT instance to search for a test pattern for detecting the set of faults. The SAT instance or the SAT solving engine may be modified so that the SAT solving engine will search for a test pattern for detecting a maximum number of faults in the set of faults.