SAT-Based Resubstitution for Incremental Logic Optimization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing methods for optimizing Boolean functions in logic circuitry, such as node resubstitution, are limited in scalability and quality, particularly in standard-cell mapped networks, as they often require explicit computation of don't-care sets and lack efficient incremental optimization techniques.
Innovation Solution
The proposed solution employs SAT-based resubstitution techniques that leverage don't-care flexibilities through windowing and SAT solving to perform incremental optimization, allowing for localized transformations and incremental remapping, thereby optimizing standard-cell mapped networks without the need for explicit don't-care set computation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If explicit don't-care set computation is used for node resubstitution, then optimization quality improves, but computational complexity and scalability deteriorate
Solution Approach 1:
The patent extracts and removes the computationally expensive explicit don't-care set computation step from the resubstitution process. Instead, it uses SAT-based reasoning to directly determine resubstitution opportunities and optimizations without explicitly constructing the don't-care sets, thereby maintaining optimization quality while reducing computational complexity
Solution Approach 2:
The patent replaces the traditional mechanical/computational approach of explicitly computing don't-care sets with a SAT-based logical reasoning system. This substitution uses satisfiability solving to indirectly determine optimization opportunities without following the explicit computational path of traditional methods, reducing complexity while preserving optimization effectiveness
2Manufacturing precision
If localized resubstitution is performed without incremental techniques, then optimization precision improves, but processing time increases
Solution Approach 1:
The patent performs preliminary identification of resubstitution opportunities using SAT-based reasoning before executing the actual resubstitution. By pre-analyzing the circuit to identify potential optimization locations and using incremental techniques to track changes, it avoids re-processing the entire circuit repeatedly, thus maintaining precision while reducing processing time
Solution Approach 2:
The patent introduces dynamic incremental techniques that allow the optimization process to adapt and track changes as resubstitution progresses. Instead of static re-analysis of the entire circuit, the system dynamically updates and focuses computation on affected regions, maintaining optimization precision while significantly reducing processing time through incremental updates
3Manufacturing precision
If comprehensive network resynthesis is performed, then overall optimization improves, but scalability deteriorates
Solution Approach 1:
The patent segments the comprehensive network resynthesis into localized resubstitution operations performed at individual nodes or small regions. By dividing the large-scale optimization problem into smaller, independent SAT-based resubstitution tasks that can be performed incrementally, it achieves comprehensive optimization effects while maintaining scalability and avoiding the computational burden of traditional full-network resynthesis approaches
Data Source
AI summary
Embodiments herein describe selecting a gate in a mapped network and then un-mapping the gate from a library cell into a Boolean expression. Resubstitution can be performed on the gate to determine whether its logic can be simplified using, e.g., a don’t care set and candidate divisors within a window of the gate. If a new Boolean expression resulting from performing resubstitution has an equivalent function, the gate can be re-mapped using the new Boolean expression, which can reduce the area of a circuit design corresponding to the mapped network. These steps can be performed iteratively on the mapped network.