SAT-Based Static Memory Allocation for Hardware-Constrained Graphs

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Solution Overview

Problem

Existing methods for static memory allocation in computational graphs, such as neural networks, fail to efficiently handle hardware-specific constraints and often require excessive computational time, especially when heuristic approaches are inadequate.

Innovation Solution

A method that splits a computational graph into subgraphs, applies an SAT solver to solve memory allocation constraints for each subgraph separately, and subdivides subgraphs into tiles to optimize memory allocation, using Boolean conditions to adapt to hardware restrictions and perform performance analysis.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If heuristic approaches are used for memory allocation, then implementation simplicity is maintained, but allocation efficiency and ability to handle hardware constraints deteriorates

Engineering Contradiction:
Improvememory allocation efficiencyVSAvoidallocation method complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The computational graph is divided into multiple subgraphs, and each subgraph is further divided into tiles. This segmentation allows the SAT solver to handle smaller, more manageable allocation problems separately, improving overall allocation efficiency while maintaining tractable complexity for each subproblem.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The SAT solver acts as an intermediary between the memory allocation problem and hardware constraints. It translates allocation requirements into Boolean satisfiability problems, enabling efficient exploration of allocation possibilities while systematically handling hardware-specific constraints that heuristic methods cannot address.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If the entire computational graph is allocated as a single unit, then global optimization is achieved, but computational time and complexity increases exponentially

Engineering Contradiction:
Improveallocation constraint satisfactionVSAvoidcomputation time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The computational graph is divided into subgraphs and further into tiles, transforming one large exponential optimization problem into multiple smaller polynomial-time problems. Each tile can be allocated independently, dramatically reducing computational time while maintaining constraint satisfaction through the SAT solver's systematic approach.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Liveness analysis is performed beforehand to determine which variables are alive at each point in the computational graph. This preliminary analysis provides constraints that guide the SAT solver, reducing the search space and enabling faster allocation without compromising global optimization.

Inventive Principle:
Principle #10Preliminary action

3Adaptability or versatility

If memory allocation ignores hardware-specific constraints, then allocation speed is maintained, but hardware compatibility and performance deteriorates

Engineering Contradiction:
Improvehardware constraint adaptabilityVSAvoidallocation speed
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The allocation method applies different constraints and parameters to different hardware configurations. Hardware-specific constraints such as memory bank organization, mode restrictions, and size limitations are incorporated into the SAT solver formulation, allowing the same framework to adapt to various hardware architectures while maintaining efficient allocation through the SAT solving approach.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS12554538B2Static memory allocation using SAT solver
Publication Date: 2026.02.17 SAMSUNG ELECTRONICS CO LTD
  • US12554538B2 patent drawing
  • US12554538B2 patent drawing
  • US12554538B2 patent drawing

AI summary

A method of statically allocating memory for a computer program includes splitting a computational graph associated with a plurality of static memory allocation constraints into a plurality of subgraphs; determining a memory allocation for each combination of subgraphs of the plurality of subgraphs using an SAT solver and a plurality of Boolean conditions that formalize the plurality of static memory allocation constraints; subdividing a subgraph of the plurality of subgraphs into a plurality of tiles, when the memory allocation for that subgraph cannot satisfy a hardware memory size constraint of the plurality of static memory allocation constraints; performing a performance analysis on all possible subgraphs and plurality of tiles; selecting a combination of subgraphs whose plurality of tiles has a best overall performance; and determining a memory allocation for the plurality of tiles for the selected combination of subgraphs using the SAT solver.