SAT-Sweeping Gate Merging via Simulation Pre-Filtering
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Solution Overview
Problem
Current SAT-sweeping techniques in electronic design automation systems inefficiently spend runtime proving non-equivalence of gates, rather than focusing on proving equivalences for synthesis, due to high computational costs and a low percentage of mergeable gates.
Innovation Solution
The system generates simulation patterns to reduce false gate candidates for merging, using a SAT-solver with a low conflict budget and approaching gates in inverse topological order, thereby reducing redundant computation and expensive SAT-solver calls.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional SAT-sweeping techniques are used to prove gate equivalence, then gate merging capability is maintained, but runtime is excessively spent on proving non-equivalence of gates
Solution Approach 1:
The patent applies preliminary action by performing simulation-based pre-filtering before SAT-solving. Simulation patterns are generated and applied to identify candidate gate pairs that are likely to be equivalent, so that only these pre-selected candidates undergo expensive SAT-solving verification. This preliminary classification step reduces the number of SAT-solver calls by eliminating obvious non-equivalent pairs early in the process.
Solution Approach 2:
The patent introduces simulation patterns as an intermediary between gate identification and SAT-solving verification. These simulation patterns serve as a mediator that pre-evaluates gate pairs using low-cost simulation before committing to expensive SAT-solving, thereby filtering out non-equivalent candidates and allowing the SAT-solver to focus only on promising equivalence proofs.
2Measurement precision
If SAT-solver is called frequently to verify gate equivalence, then accuracy in identifying mergeable gates is maintained, but computational cost increases
Solution Approach 1:
The patent applies local quality by using different verification strategies for different gate pairs based on their characteristics. Not all gate pairs undergo full SAT-solving verification; instead, simulation-based pre-filtering is applied locally to each candidate pair, and only those passing the simulation test proceed to SAT-solving. This localized application of verification resources optimizes the balance between accuracy and computational cost.
3Productivity
If all gate pairs are evaluated for merging potential, then comprehensive gate merging is achieved, but redundant computation occurs
Solution Approach 1:
The patent segments the gate evaluation process into distinct phases: simulation-based pre-filtering phase and SAT-solving verification phase. This segmentation divides the comprehensive gate pair evaluation into manageable stages, where the first stage quickly filters candidates and the second stage performs detailed verification only on filtered candidates, eliminating redundant computation while maintaining comprehensive coverage.
Solution Approach 2:
The patent applies partial action by performing simulation-based evaluation on all gate pairs (partial filtering) rather than exhaustive SAT-solving on all pairs. This partial application of verification—using simulation for all candidates and reserving SAT-solving for selected candidates—reduces redundant computation while still achieving comprehensive gate merging through the two-stage process.
Data Source
AI summary
A system and method for SAT-sweeping is disclosed. According to one embodiment, a method includes determining gate classes by inputting simulation patterns to gates in an integrated circuit design, selecting a candidate gate based on an inverse topological ordering of the gates, and then selecting a driver gate belonging to the same gate class as the candidate gate. A SAT-solver is called based on the candidate gate and the driver gate to confirm equivalence. The candidate gate and the driver gate are then merged in the integrated circuit design.