Boolean Satisfiability for IC Timing Exception Verification
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Solution Overview
Problem
Existing IC design verification techniques are inefficient and error-prone in verifying sequential false paths and multi-cycle paths, particularly due to their inability to handle complex logic paths and long verification times.
Innovation Solution
A method and system that model false paths and multi-cycle paths as satisfiability formulas, using Boolean satisfiability solvers to validate these paths, significantly reducing verification time by transforming paths into XOR operations and using Boolean satisfiability solvers like SAT, ATPG, or BDD.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If timing simulation, static timing analysis, or functional timing analysis is used to verify false paths and multi-cycle paths, then verification coverage is achieved, but verification time becomes excessively long and errors increase
Solution Approach 1:
The patent replaces traditional timing verification methods (simulation, static timing analysis, functional timing analysis) with a Boolean satisfiability-based approach. By transforming timing exception verification into a SAT problem, the invention substitutes mechanical/physical verification processes with logical/mathematical computation, achieving both accuracy and efficiency simultaneously
Solution Approach 2:
The patent changes the fundamental parameter of verification from temporal-based (simulation time, clock cycles) to logical-based (Boolean satisfiability). This parameter transformation allows the verification to be performed in discrete logical steps rather than continuous time consumption, resolving the contradiction between verification thoroughness and time consumption
2Reliability
If traditional verification methods are used to handle complex logic paths, then comprehensive verification is attempted, but error rate increases and efficiency decreases
Solution Approach 1:
The patent substitutes traditional mechanical verification processes with Boolean satisfiability solving. By representing timing exceptions as SAT formulas and using systematic solving algorithms, the invention achieves complete verification coverage while maintaining high efficiency through logical computation rather than exhaustive simulation or analysis
Solution Approach 2:
The patent creates a logical copy of the timing exception verification problem in the form of a SAT formula. This abstract representation allows the verification to be performed on the logical model rather than the actual circuit, maintaining completeness while dramatically improving efficiency through mathematical solving techniques
Data Source
AI summary
A method and system for timing exception verification in integrated circuit (IC) designs included verification of functional false paths as well as multi-cycle paths (MCPs). A false path or a MCP is modeled to a satisfiability formula and the formula is validated using a Boolean satisfiability solver. Time required for timing exception verification can be significantly reduced.