SATA Device Intra-Command Processing via RXRDY Flag

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Solution Overview

Problem

The existing SATA protocol's requirement for delays between block transfers in read commands significantly degrades the performance of SATA devices by preventing the host from sending intra-command data during ongoing operations, such as unloading a disk drive's actuator arm to avoid damage from free falls.

Innovation Solution

Modifying the SATA device's Link layer state transition diagram to set a RXRDY flag when receiving a XRDY primitive in the XRDY state, allowing the host to transmit intra-command data during the IDLE state, enabling the processing of additional commands without interrupting the current read operation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a delay is inserted between each block transfer to allow the host to send intra-command data, then the host can send intra-command data during ongoing operations, but the throughput of the SATA device is significantly degraded

Engineering Contradiction:
Improveability to send intra-command dataVSAvoidthroughput
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent applies dynamics by making the state transition diagram responsive to incoming XRDY primitives. The system dynamically adjusts its behavior based on real-time conditions - when a XRDY primitive is received during IDLE state, the system transitions to processing intra-command data; otherwise, it continues with the current read operation. This dynamic adaptation allows the system to handle both throughput and intra-command data transmission without fixed delays.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent implements preliminary action by having the SATA device wait in the IDLE state for incoming XRDY primitives before transitioning to data processing. This preliminary waiting period allows the host to send intra-command data when needed, without forcing continuous delays during actual data transmission. The device prepares to handle intra-command data at the appropriate moment rather than continuously blocking.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If the SATA device waits for RRDY primitive in XRDY state, then data transmission can proceed, but the host cannot send intra-command data during ongoing operations

Engineering Contradiction:
Improvedata transmission efficiencyVSAvoidability to receive intra-command data
Core Design Contradiction:
ProductivityVSAdaptability or versatility

Solution Approach 1:

The patent segments the state transition process into distinct phases: the primary read operation phase (XRDY state) and the intra-command data processing phase (IDLE state with XRDY primitive reception). By segmenting these functions into separate state paths, the system can efficiently handle data transmission during XRDY state while also providing a separate pathway for receiving intra-command data during IDLE state, resolving the mutual exclusion problem.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces the IDLE state as an intermediary between the XRDY state and the final data processing. This intermediary state serves as a buffer where the SATA device can receive XRDY primitives from the host during ongoing read operations. The intermediary IDLE state allows both functions to coexist - the primary read operation continues in the background while intra-command data can be received and processed when needed.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS7827320B1Serial ATA device implementing intra-command processing by detecting XRDY primitive while in the XRDY state
Publication Date: 2010.11.02 WESTERN DIGITAL TECHNOLOGIES INC
  • US7827320B1 patent drawing
  • US7827320B1 patent drawing
  • US7827320B1 patent drawing

AI summary

A Serial Advanced Technology Attachment (SATA) device for communicating with a host is disclosed. The SATA device comprises control circuitry which enters a XRDY state in preparation for sending data to the host, receives a first XRDY from the host while in the XRDY state, and sets a RXRDY flag. After receiving the first XRDY, the control circuitry receives a RRDY from the host while in the XRDY state, transmits a data block to the host in response to the RRDY, and enters an idle state after transmitting the data block to the host. If the RXRDY flag is set while in the idle state, the control circuitry waits for the host to transmit a second XRDY.