Satellite Software Verification Using Parallel Memory Data Analysis

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Solution Overview

Problem

Current satellite software verification methods are time-consuming and limited in scope due to the need for sequential receipt of telemetry frames, which restricts the thoroughness of verification and increases development costs.

Innovation Solution

A satellite software verification method and system that utilizes a simulator to receive memory data in a high-data-rate communication mode, generates and analyzes telemetry frames, and performs additional analysis on all items except those in the frames, allowing for quicker verification of main items and obtaining information beyond what's available in telemetry frames, thereby simulating a real environment for verification.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If data is received sequentially from a simulator in traditional communication mode, then verification accuracy is maintained, but verification time increases significantly

Engineering Contradiction:
Improveverification accuracyVSAvoidverification time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent segments the verification process into two parallel paths: (1) receiving and analyzing telemetry frames through the communication unit in traditional mode, and (2) directly accessing and analyzing memory data through the processor in high-speed mode. This segmentation allows simultaneous execution of both verification methods, maintaining accuracy while reducing time loss.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces memory data as an intermediary element that bridges the traditional communication path and the accelerated verification path. By accessing the simulator's memory data directly, the system obtains verification information without waiting for sequential telemetry frame transmission, thus reducing verification time while maintaining accuracy through cross-validation.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If all verification items are checked through sequential telemetry frames, then comprehensive verification is achieved, but development cost increases

Engineering Contradiction:
Improveverification thoroughnessVSAvoiddevelopment cost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent applies partial action by performing comprehensive verification on critical items through direct memory data analysis, while using sequential telemetry frame reception for less critical verification items. This selective approach ensures thorough verification of essential functions without incurring the full cost of exhaustive sequential verification on all items.

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The patent changes the verification parameter from sequential frame-by-frame analysis to parallel memory-based analysis for critical items. This parameter change enables faster verification of key reliability aspects, reducing overall development time and cost while maintaining thoroughness through targeted verification of critical systems.

Inventive Principle:
Principle #35Parameter changes

3Loss of information

If verification waits for complete telemetry frame reception, then data completeness is ensured, but productivity decreases

Engineering Contradiction:
Improvedata completenessVSAvoidverification speed
Core Design Contradiction:
Loss of informationVSProductivity

Solution Approach 1:

The patent performs preliminary action by directly accessing memory data before telemetry frames are fully received and processed. This allows verification to begin in advance based on available memory information, improving productivity while data completeness is subsequently confirmed through comparison with received telemetry frames.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback by continuously comparing results from direct memory data analysis with results from sequential telemetry frame analysis. This feedback mechanism ensures data completeness is maintained while allowing accelerated verification through the high-speed memory access path, as discrepancies can be detected and corrected through cross-validation.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS10467125B2Satellite software verification system
Publication Date: 2019.11.05 KOREA AEROSPACE RES INST
  • US10467125B2 patent drawing
  • US10467125B2 patent drawing
  • US10467125B2 patent drawing

AI summary

Provided is a method of verifying satellite software using a simulator, the method including receiving memory data of the simulator from the simulator in a first communication mode, the simulator being loaded with the satellite software to be verified; generating a first telemetry frame from the memory data based on a telemetry frame generation rule; and analyzing the first telemetry frame.