TDD Scheduling in Satellite FDD Networks for Half-Duplex UEs

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Solution Overview

Problem

In satellite communications systems, the large propagation delay introduces significant overhead due to the need for large gap periods in time division duplexing (TDD), leading to inefficient use of network resources when using half duplex user equipment (UE).

Innovation Solution

Implementing a full duplex gateway terminal with a scheduler that accounts for propagation delays to allocate downlink (DL) and uplink (UL) time slots efficiently, avoiding overlaps at half duplex UE while allowing overlaps at the gateway, thus optimizing network resource utilization.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If time division duplexing is used in satellite communications systems with half duplex user equipment, then the system can operate with simpler UE hardware, but the large propagation delay requires large gap periods causing significant overhead and inefficient network resource utilization

Engineering Contradiction:
ImproveUE hardware complexityVSAvoidnetwork resource utilization
Core Design Contradiction:
Ease of manufactureVSProductivity

Solution Approach 1:

The system segments the communication into distinct downlink and uplink time slots with precise timing control. By dividing the communication cycle into separate transmission phases and using timing advance mechanisms, the system eliminates the need for large gap periods while maintaining half-duplex UE simplicity, thereby resolving the contradiction between hardware simplicity and resource utilization efficiency

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system applies preliminary timing adjustment by advancing uplink transmissions at UE side before the actual communication occurs. This timing advance compensates for propagation delay in advance, allowing the gateway to schedule downlink and uplink slots without requiring large gaps, thus improving network resource utilization while keeping UE hardware simple

Inventive Principle:
Principle #10Preliminary action

2Productivity

If frequency division duplexing is used with full duplex gateway terminal and half duplex UE, then network resource utilization is optimized, but the system complexity increases due to propagation delay compensation requirements

Engineering Contradiction:
Improvenetwork resource utilizationVSAvoidscheduling system complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The system introduces a scheduler as an intermediary component that mediates between the gateway terminal and UE. This scheduler handles the propagation delay compensation and timing coordination, abstracting the complexity from the individual devices. The scheduler calculates appropriate timing advances and slot allocations, enabling efficient resource utilization while managing system complexity through a dedicated coordination layer

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The system implements dynamic timing adjustment where uplink time slots are advanced based on actual propagation delay conditions. Rather than using fixed large gaps, the system dynamically adapts the timing of uplink transmissions to match the downlink schedule, optimizing resource utilization while managing complexity through flexible timing control mechanisms

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS20250317878A1Using time division duplexing systems in frequency division duplexing networks
Publication Date: 2025.10.09 VIASAT INC
  • US20250317878A1 patent drawing
  • US20250317878A1 patent drawing
  • US20250317878A1 patent drawing

AI summary

Described herein are technologies that utilize full duplex gateway terminals in satellite networks with half duplex user equipment. The disclosed scheduling technologies incorporate the knowledge of the propagation delay between a gateway terminal and each UE in communication with the gateway terminal. Based on this propagation delay, a scheduler can allocate DL and UL time slots in a scheduling frame in a way that avoids allocating overlapping DL and UL time slots at each UE.