Saturating Event Counter for Processor Performance Monitoring

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Solution Overview

Problem

Conventional performance monitoring systems face issues with counter overflow and misrepresentation of performance data due to the need for frequent counter resets and lack of temporal distribution information in processor performance measurements.

Innovation Solution

The implementation of saturating counters that increment upon detecting performance-related events and decrement during event-free periods, providing a relative frequency indication without overflow errors and offering temporal performance analysis.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If conventional counters are used to measure performance events, then the count values can indicate the number of events occurred, but counter overflow occurs when a large number of events occur, leading to erroneous low count values

Engineering Contradiction:
Improveperformance measurement accuracyVSAvoidcounter overflow error
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The counter transitions from a static fixed-width register to a dynamic structure that automatically expands when overflow is detected. The system monitors for overflow conditions and dynamically allocates additional counter registers to accommodate larger event counts, thereby maintaining measurement accuracy without requiring manual intervention or reset operations.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

An overflow detection mechanism acts as an intermediary between the event counter and the measurement system. This intermediary monitors the counter state, detects overflow conditions, and triggers appropriate responses such as expanding the counter width or alerting the system, thereby preventing erroneous measurements without affecting the core counting function.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If counters are periodically reset to prevent overflow, then overflow errors are avoided, but temporal distribution information of performance events is lost

Engineering Contradiction:
Improvecounter overflow preventionVSAvoidtemporal distribution information
Core Design Contradiction:
ReliabilityVSLoss of information

Solution Approach 1:

The system performs preliminary overflow detection before actual overflow occurs by monitoring the counter state continuously. When the counter approaches its maximum value, the system proactively expands the counter width or allocates additional storage, preventing overflow before it can corrupt temporal information about event distributions.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The solution adds an additional dimension to the counter by transitioning from a single fixed-width register to a multi-register structure or variable-width counter. This dimensional expansion provides both overflow prevention and preservation of temporal event distribution information, as the extended counter width can accommodate longer event sequences without reset.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Device complexity

If fixed-width counters are used, then the device complexity is low, but the counters cannot accommodate large numbers of events without overflow

Engineering Contradiction:
Improvecounter structure simplicityVSAvoidevent count range
Core Design Contradiction:
Device complexityVSMeasurement precision

Solution Approach 1:

The counter system dynamically adjusts its width based on the number of events detected. Starting with a simple fixed-width counter, the system automatically expands to wider counters or multi-register structures when event counts exceed the initial capacity, thereby maintaining both simplicity for normal operation and precision for large event volumes.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The counter width parameter is made variable rather than fixed. The system changes the counter width parameter dynamically based on the observed event rate and total event count, allowing the counter to maintain optimal precision for the current workload while avoiding the need for a unnecessarily complex wide counter from the start.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS10169187B2Processor core having a saturating event counter for making performance measurements
Publication Date: 2019.01.01 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US10169187B2 patent drawing
  • US10169187B2 patent drawing
  • US10169187B2 patent drawing

AI summary

A performance monitor including a saturating counter provides a relative measure of event frequency without requiring a minimum polling rate or periodic reset to avoid or account for counter overflow. The saturating counter is incremented upon detection of an event and decremented if an event is not detected within a predetermined period. The period of detecting may be programmable and may be determined by real time clock, processor or instruction cycles. Multiple event types may be selected from for detection and input to a single counter, or alternatively multiple event counters may be provided for various event types. The saturating counter may additionally be periodically reset in a selected operating mode, in combination with the decrementing action performed on the counter.