SAW Package Layout With Pillar Electrodes for Lower Parasitic Capacitance
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Solution Overview
Problem
Conventional SAW devices face issues with larger package sizes and increased parasitic capacitance, which hinder miniaturization and performance, while the need for more IDT finger pairs generates heat instability.
Innovation Solution
The SAW device design incorporates pillar-shaped electrodes protruding from the cover layer and supportive layer, reducing the package area to match the transducer space and enhancing heat dissipation, thereby minimizing parasitic capacitance and improving performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the package size is reduced to meet miniaturization requirements, then the device becomes more compact, but the space for receiving IDT finger pairs is reduced, limiting performance improvement
Solution Approach 1:
The patent utilizes the vertical dimension by forming pillar-shaped electrodes that protrude from the lateral surface of the cover layer. This three-dimensional structure allows electrical connections to extend outward, enabling compact planar layout while maintaining adequate spacing and reducing parasitic capacitance effects that would otherwise limit IDT finger pair density.
Solution Approach 2:
The pillar-shaped electrodes are formed by extending conductive structures through multiple layers (supportive layer and cover layer), creating a nested configuration where conductive elements are embedded within the package structure. This nested arrangement optimizes space utilization, allowing more IDT finger pairs to be accommodated within the reduced package footprint.
2Productivity
If more IDT finger pairs are added to improve SAW generation and frequency response, then performance increases, but the device size must increase to accommodate the larger transducer space
Solution Approach 1:
By transitioning from planar electrode connections to three-dimensional pillar structures, the patent frees up planar space that can be reallocated to accommodate additional IDT finger pairs, thereby improving frequency response without proportionally increasing device area.
Solution Approach 2:
The use of thin supportive and cover layers with integrated pillar electrodes creates a compact structure that maximizes the ratio of functional area to overall device area, allowing higher density of IDT finger pairs within constrained dimensions.
3Productivity
If more IDT finger pairs are added to enhance performance, then heat generation increases, but heat dissipation becomes insufficient, causing instability
Solution Approach 1:
The pillar-shaped electrodes protrude from the cover layer to provide dedicated heat dissipation pathways. This extraction of conductive elements to the surface creates thermal conduction channels that extend from the heat-generating IDT region through the pillar structures, improving heat removal capability independent of device footprint.
Solution Approach 2:
The pillar-shaped electrodes serve as intermediary thermal conduction paths between the IDT and the external environment. These structures act as thermal mediators that facilitate heat transfer from the embedded transducer elements to the package exterior, enabling effective thermal management for high-density IDT configurations.
4Reliability
If conventional bump structures are used in via holes, then electrical connection is achieved, but parasitic capacitance increases and package area exceeds transducer space
Solution Approach 1:
The patent transitions from planar bump structures confined to via holes to three-dimensional pillar electrodes that extend laterally from the cover surface. This dimensional change reduces the overlapping area between conductive elements and adjacent signal lines, thereby minimizing parasitic capacitance while maintaining reliable electrical connections.
Solution Approach 2:
By extracting the electrode structures from the confined via hole geometry and extending them outward as pillar shapes, the patent reduces the capacitive coupling between signal lines and ground planes. The protruding configuration minimizes the effective area for parasitic capacitance formation while preserving electrical connectivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves reduced parasitic capacitance, increased transducer capacity, and improved heat dissipation, resulting in a smaller package size with enhanced performance and stability.
Implementation Method 1
surface acoustic wave (SAW) device... piezoelectric substrate 210... interdigital transducer (IDT) 213
Data Source
Figure 1
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Figure 4~5
AI summary
A surface acoustic wave device (100) includes a piezoelectric substrate (111), a supportive layer (120), a cover layer (130) and a pillar bump (150). The supportive layer is disposed on the piezoelectric substrate and around a transducer, the cover layer covers the supportive layer, and the pillar bump is located in a lower via hole of the supportive layer and an upper via hole of the cover layer. The upper via hole has a lateral opening located on a lateral surface of the cover layer, and the pillar bump in the cover layer protrudes from the lateral surface of the cover layer via the lateral opening.