SAW Package Via Layout for Short Signal Paths and Lower Stress

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Solution Overview

Problem

Existing elastic wave devices, such as wafer-level package (WLP) devices, face challenges in efficiently integrating terminals and conductive layers to enhance signal filtering and transmission while maintaining structural integrity and thermal stability.

Innovation Solution

The elastic wave device incorporates a piezoelectric substrate with excitation electrodes, a cover, and via conductors of varying diameters, along with a conductive reinforcement layer, to facilitate efficient signal transmission and filtering, and includes a duplexer and communication device configurations to optimize performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If via conductors are arranged close to the outer periphery of the piezoelectric substrate to reduce the number of layers, then device complexity is reduced, but stress concentration and structural defects increase

Engineering Contradiction:
Improvenumber of layersVSAvoidstructural defects
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent transitions from a planar two-dimensional arrangement of via conductors to a three-dimensional stacked configuration. Multiple via conductors are arranged in different layers at different positions on the piezoelectric substrate, allowing signal transmission paths to be routed through vertical stacking rather than requiring closely-spaced lateral arrangements. This dimensional change enables reduced layer count while maintaining adequate spacing between via conductors to prevent stress concentration and structural defects.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Speed

If via conductors are arranged close to the outer periphery to shorten signal transmission distance, then transmission efficiency is improved, but stress concentration increases

Engineering Contradiction:
Improvesignal transmission distanceVSAvoidstress concentration
Core Design Contradiction:
SpeedVSStress or pressure

Solution Approach 1:

The patent utilizes vertical stacking of via conductors in multiple layers to shorten the lateral distance from the outer periphery of the piezoelectric substrate to the signal transmission path. By routing signals through vertically-stacked via conductors rather than requiring closely-spaced lateral arrangements, the invention achieves short transmission distances while maintaining adequate spacing between via conductors, thereby preventing stress concentration in the substrate.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Reliability

If via conductors are spaced far apart to reduce stress concentration, then structural reliability is improved, but the number of layers increases

Engineering Contradiction:
Improvestress distributionVSAvoidnumber of layers
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent resolves the contradiction between via conductor spacing and layer count by transitioning to a three-dimensional stacked configuration. Via conductors are arranged in multiple layers at different positions on the piezoelectric substrate, allowing adequate lateral spacing between via conductors to prevent stress concentration while maintaining a compact overall structure. The vertical stacking enables signal transmission across multiple layers without requiring excessive lateral separation, thus balancing structural reliability with device complexity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

4Productivity

If via conductors are arranged to optimize signal filtering, then transmission efficiency is improved, but manufacturing precision requirements increase

Engineering Contradiction:
Improvesignal filtering efficiencyVSAvoidvia conductor positioning
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent divides the via conductor arrangement into multiple discrete layers, with each layer containing via conductors at specific positions on the piezoelectric substrate. This segmentation allows for optimized signal filtering through the stacked configuration while enabling standardized manufacturing processes for each layer. The modular layered structure facilitates precise positioning through repeated manufacturing steps, reducing overall manufacturing precision requirements compared to attempting to create complex non-layered patterns in a single step.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration enhances the reliability and thermal stability of the elastic wave device, improving signal filtering and transmission efficiency while reducing the likelihood of structural defects and stress concentrations.

Implementation Method 1

a piezoelectric substrate, at least one excitation electrode located on an upper surface of the piezoelectric substrate

Methodology Applied
Scientific EffectPiezoelectric effect: Piezoelectric Effect

Data Source

PatentUS11031919B2Elastic wave device, duplexer, and communication device
Publication Date: 2021.06.08 KYOCERA CORP
  • US11031919B2 patent drawing
  • US11031919B2 patent drawing
  • US11031919B2 patent drawing

AI summary

A surface acoustic wave (SAW) device includes a piezoelectric substrate, an interdigital transducer (IDT) electrode located on an upper surface of the piezoelectric substrate, a cover covering the upper surface of the piezoelectric substrate from above the IDT electrode, at least one first via conductor extending through at least part of the cover from the upper surface of the piezoelectric substrate to an upper surface of the cover, at least one second via conductor located, on the piezoelectric substrate, inward from the first via conductor in a plan view, extending through at least part of the cover from the upper surface of the piezoelectric substrate to the upper surface of the cover, and having a smaller diameter than the first via conductor, and a conductive layer located on the upper surface of the cover and extending over an upper end of the second via conductor.