Sawtooth High-Voltage Transistor Structure for Lower NBTI
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Solution Overview
Problem
High-voltage transistors are affected by negative bias temperature instability (NBTI), which shifts the threshold voltage and reduces the service life, and increasing the gate dielectric layer thickness to mitigate this also reduces the driving current, posing a challenge in balancing NBTI reduction with performance.
Innovation Solution
A high-voltage transistor device with a semiconductor substrate featuring a sawtooth sectional profile and an isolation structure, where the gate dielectric layer is partially filled in grooves, allowing for a longer channel width without reducing the gate dielectric layer thickness, thereby reducing NBTI and enhancing driving current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the thickness of the gate dielectric layer is increased to reduce NBTI, then the reliability is improved, but the driving current is reduced
Solution Approach 1:
The patent introduces a third dimension by forming grooves in the semiconductor substrate and partially filling them with gate dielectric material. This vertical dimension allows the gate dielectric layer to extend into the grooves, increasing the effective channel width without increasing the planar footprint. The gate dielectric thickness is maintained at optimal levels while the multi-dimensional structure provides enhanced NBTI resistance through increased surface area and improved stress distribution.
Solution Approach 2:
The gate dielectric layer is segmented into different regions: some portions are formed in the grooves while other portions are formed on the flat substrate surface. This segmentation allows different regions to serve different functions - the groove-filled regions provide enhanced NBTI resistance while maintaining appropriate dielectric thickness, and the overall structure increases the effective channel width for higher driving current.
2Duration of action of stationary object
If the thickness of the gate dielectric layer is increased to reduce NBTI, then the service life is improved, but the device efficiency is reduced
Solution Approach 1:
By extending the gate dielectric layer into the grooves formed in the semiconductor substrate, the patent increases the effective channel width in the vertical dimension. This allows the device to maintain optimal gate dielectric thickness for NBTI resistance while achieving higher driving current and efficiency through the increased effective width provided by the three-dimensional structure.
Solution Approach 2:
The gate dielectric layer is selectively formed in different regions - within the grooves and on the flat substrate surface. This local differentiation allows the structure to optimize both NBTI resistance (through the groove-filled regions with appropriate dielectric thickness) and device efficiency (through the increased effective channel width from the overall multi-dimensional structure).
Data Source
AI summary
A high-voltage transistor device includes a semiconductor substrate, an isolation structure, a gate dielectric layer, a gate, a source region and a drain region. The semiconductor substrate has a plurality of grooves extending downward from a surface of the semiconductor substrate to form a sawtooth sectional profile. The isolation structure is disposed on the outside of the plurality of grooves, and extends from the surface downwards into the semiconductor substrate to define a high-voltage area. The gate dielectric layer is disposed on the high-voltage area and partially filled in the plurality of grooves. The gate is disposed on the gate dielectric layer. The source region and the drain region are respectively disposed in the semiconductor substrate and isolated from each other.