Sb-Pt Contacts for WSe2 FETs With Tunable Work Function
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Solution Overview
Problem
The short channel effect in transistors, characterized by an increase in off-state current with reduced channel length, hinders further integration density improvements in semiconductor devices. Additionally, the Fermi level pinning and unsatisfactory band alignment at the Pd-WSe2 junction in 2D semiconductor devices compromise their performance.
Innovation Solution
The use of antimony (Sb) and platinum (Pt) as source/drain contacts in 2D semiconductor devices, where the Sb layer interfaces with the WSe2 layer and the Pt layer is over the Sb layer, mitigates Fermi level pinning and allows for tunable effective work function by varying the thickness ratio of Sb to Pt.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If channel length is reduced to improve integration density, then more components can be integrated into a given area, but off-state current increases due to short channel effect
Solution Approach 1:
The patent changes the material parameter of the contact layer from conventional metal to two-dimensional material (such as graphene, transition metal dichalcogenides), which fundamentally alters the electrical characteristics at the contact interface. This material parameter change enables better control of off-state current while maintaining low contact resistance, thus resolving the short channel effect issue and allowing continued scaling for improved integration density
2Ease of manufacture
If Pd-WSe2 junction is used for source/drain contacts, then fabrication is simplified, but Fermi level pinning and unsatisfactory band alignment compromise device performance
Solution Approach 1:
The patent introduces a two-dimensional material layer as an intermediary between the metal contact and the WSe2 semiconductor channel. This intermediate layer acts as a mediator that improves band alignment and reduces Fermi level pinning effects, thereby enhancing contact performance while maintaining the simplicity of the fabrication process. The 2D material serves as a buffer that optimizes the electrical interface without complicating the manufacturing steps
Data Source
AI summary
A device includes a first 2D semiconductor layer over a substrate, a first source/drain contact interfacing a first region of the first 2D semiconductor layer, and a second source/drain contact interfacing a second region of the first 2D semiconductor layer spaced apart from the first region of the first 2D semiconductor layer. The first source/drain contact includes an antimony layer interfacing the first region of the first 2D semiconductor layer, and a platinum layer over the antimony layer.