System Basis Chip Power State Coordination
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Solution Overview
Problem
In split-PHY architectures, where the PHY transceiver and PHY controller are implemented separately, there is a challenge in managing coordinated power states and power state transitions, leading to inefficiencies, increased power consumption, and operational anomalies such as unintended wake-ups or failures to enter low-power states correctly.
Innovation Solution
A system basis chip (SBC) is designed to coordinate changes in power states with the PHY transceiver by implementing a hardware interface between the PHY transceiver and PHY controller, using a finite-state-machine (FSM) to stage power state changes, ensuring that both the SBC and PHY transceiver change power states concurrently, thereby managing power states synchronously.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the PHY transceiver and PHY controller are implemented separately in split-PHY architectures, then device functionality and flexibility are improved, but power state coordination becomes complex and prone to operational anomalies
Solution Approach 1:
A hardware interface is introduced as an intermediary between the PHY transceiver and PHY controller to coordinate power state transitions. This interface includes synchronization logic that mediates the power state changes, ensuring both components transition concurrently and avoiding operational anomalies while maintaining the benefits of separate implementation.
2Ease of operation
If power state changes are managed without coordination between SBC and PHY transceiver, then device operation simplicity is improved, but power consumption increases and system instability occurs
Solution Approach 1:
The power state management of the SBC and PHY transceiver is merged through a coordinated transition mechanism. The hardware interface ensures that power state changes are synchronized between both components, allowing them to transition together to low-power states efficiently, thereby reducing overall power consumption while maintaining simple operation through unified management.
3Speed
If power state transitions are abrupt without staging, then transition speed is improved, but system stability deteriorates and operational anomalies increase
Solution Approach 1:
The hardware interface performs preliminary actions by staging power state transitions before they are fully executed. This involves preparing both the SBC and PHY transceiver for power state changes in a coordinated manner, ensuring that necessary conditions are met before transitioning, which maintains system stability while achieving efficient transition speeds.
Data Source
AI summary
A method includes providing a system basis chip that supports at least two power states: a sleep state and an awake state; monitoring for power state information via a hardware interface and via a communication interface, wherein the hardware interface allows communication between a physical layer (PHY) transceiver implemented at the system basis chip and a PHY controller implemented at a microcontroller, and wherein the communication interface allows communication between the system basis chip and the microcontroller; and coordinating a change in power state of the system basis chip at least partially based on reception of power state information via the hardware interface and the communication interface.