Shallow Buried Guard Ring Layout for CMOS Latchup Immunity
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Solution Overview
Problem
CMOS integrated circuits face reliability issues due to high resistivity in silicon regions, leading to latchup and permanent damage from overvoltage or radiation-induced transient upsets, especially at extreme temperatures.
Innovation Solution
The implementation of a Shallow Buried Guard Ring (SBGR) structure using high dose/high energy ion implants and masking to form low resistivity P-type doping regions within PWELL regions, reducing silicon resistivity and minimizing ion implant defects, thereby preventing latchup and ensuring reliable operation across a wide temperature range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high resistivity PWELL regions are used for isolation, then electrical isolation is improved, but latchup susceptibility increases
Solution Approach 1:
The patent applies local quality by creating a P+ doped guard ring structure with specific local properties (high doping concentration, shallow depth) within the PWELL region. This localized doped region provides low resistivity path for current diversion while maintaining the overall isolation function, resolving the contradiction between electrical isolation and latchup immunity.
Solution Approach 2:
The patent changes the doping parameter by introducing a P+ doped region with high doping concentration (1E19 to 1E21 atoms/cm³) at a shallow depth (0.5 to 2.0 micrometers) within the PWELL. This parameter change creates a low resistivity region that prevents latchup while maintaining isolation, resolving the contradiction between resistivity control and latchup immunity.
2Manufacturing precision
If multiple ion implants are used to form SBGR, then doping precision is improved, but process complexity increases
Solution Approach 1:
The patent segments the doping process into multiple ion implantation steps with different energies and doses. The first implant uses high energy (1.0 MeV) for deep junction formation, while the second implant uses lower energy (0.5 MeV) for precise guard ring doping. This segmentation allows precise control of doping concentration profiles while managing process complexity through systematic step division.
Solution Approach 2:
The patent performs preliminary masking and alignment preparations before ion implantation. The guard ring pattern is defined using photolithography masks that are prepared in advance, and the implantation parameters (energy, dose, angle) are pre-calculated and set. This preliminary action ensures precise doping concentration control while streamlining the actual implantation process.
3Reliability
If high dose ion implants are used to reduce resistivity, then current conduction is improved, but ion implant defects increase
Solution Approach 1:
The patent utilizes phase transitions through high-temperature annealing (900°C to 1100°C for 30 to 120 seconds) after ion implantation. This thermal treatment causes phase transition in the silicon lattice, enabling defect recovery and dopant activation. The annealing process transforms the damaged crystalline structure back to its original state while activating the dopant atoms for electrical conduction, thus resolving the contradiction between current conduction improvement and defect reduction.
Solution Approach 2:
The patent converts the harmful effect of ion implantation (lattice damage and defects) into a beneficial outcome by using the implanted ions as dopant sources. The high-dose ion implants that initially create defects are subsequently activated through annealing to provide the desired high concentration P+ doping. The harmful lattice damage is transformed into beneficial dopant activation, achieving low resistivity while managing defect effects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The SBGR structure effectively prevents latchup and ensures reliable operation of CMOS devices in extreme environments by reducing resistivity and enhancing current conduction, preventing permanent damage from transient upsets and radiation exposure.
Implementation Method 1
multiple boron implants, masked over a photoresist, to form a high concentration P+ doped region
Implementation Method 2
high temperature annealing, to dissolve implant defects
Data Source
AI summary
A CMOS inverter modified by implementing p-type doping regions in the inverter layout and during semiconductor wafer manufacturing creating a novel low resistivity shunt region in PWELLs preventing parasitic thyristor diodes from forward bias and eliminating latchup triggering. Latchup trigger can only occur when all thyristor diodes forward biased thereby establishing the parasitic current flow causing latchup. As voltage scales lower and temperature increases, latchup trigging doesn't recover and leads to a “non-destructive stuck state” in addition to catastrophic latch-up. The root cause of latch-up is high resistivity PWELLs. Shallow Buried Guard Ring (SBGR) doping application is a novel solution that solves the “stuck state” and prevents latchup thereby enabling digital circuits to operate in the most extreme environments without latching up and can be integrated without redesigning and through retrofit in commercial CMOS as well as in solar power procurement through photovoltaic cells.