S-Box Synchronization Circuit for Glitch-Free Threshold Implementation
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Solution Overview
Problem
Existing synchronization circuits for threshold implementation operations in encryption circuits, such as AES, face challenges in reducing area, power consumption, and cost, while also dealing with signal delay glitches that can lead to information leakage during side-channel attacks like differential power analysis.
Innovation Solution
A synchronization circuit comprising an enable signal generator, a synchronization unit with AND gates and XOR gates, and an initialization circuit, which uses flip-flops and critical path replica circuits to generate and synchronize signals within the S-box, reducing complexity and power consumption, and eliminating signal delay glitches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a synchronization circuit is implemented for threshold implementation operations in an S-box, then signal synchronization and security against side-channel attacks are improved, but circuit area, power consumption, and cost increase
Solution Approach 1:
The synchronization circuit is divided into multiple independent components: an enable signal generator that produces synchronization signals, and a synchronization unit that applies these signals to coordinate threshold implementation operations. This segmentation allows each component to be optimized independently, reducing overall circuit area while maintaining synchronization functionality.
Solution Approach 2:
The enable signal generator uses a critical path replica circuit that copies the timing characteristics of the main computation path. By replicating only the critical timing path rather than the entire circuit, the synchronization mechanism achieves accurate signal coordination with minimal additional area overhead.
2Reliability
If a synchronization circuit is implemented for threshold implementation operations in an S-box, then signal synchronization and security against side-channel attacks are improved, but power consumption increases
Solution Approach 1:
The enable signal generator produces periodic synchronization signals based on the critical path delay characteristics. By generating enable signals only when needed (periodically rather than continuously), the circuit achieves signal synchronization while minimizing unnecessary switching activity and associated power consumption.
Solution Approach 2:
The critical path replica circuit copies only the essential timing characteristics needed for synchronization, avoiding full replication of the computation circuit. This selective copying reduces the number of active transistors and switching elements, thereby reducing power consumption while maintaining synchronization accuracy.
3Reliability
If complex synchronization circuits are used to eliminate signal delay glitches, then security against side-channel attacks is improved, but device complexity increases
Solution Approach 1:
The enable signal acts as an intermediary that coordinates the timing of threshold implementation operations. Instead of directly synchronizing multiple complex signal paths, the enable signal mediates the timing of operations, simplifying the overall circuit structure while effectively eliminating signal delay glitches that could lead to information leakage.
Solution Approach 2:
The critical path replica circuit creates a simplified copy of the timing characteristics needed for synchronization. By copying only the essential timing behavior rather than the full computational logic, the circuit achieves glitch-free operation with reduced complexity compared to fully replicated synchronization approaches.
Data Source
AI summary
This application relates to a synchronization circuit for synchronizing signals used in a threshold implementation operation process performing in an S-box of an encryption circuit. In one aspect, the synchronization circuit includes an enable signal generator configured to generate an enable signal. The synchronization circuit may also include a synchronization unit included in an encryption circuit and located inside an S-box that performs a threshold implementation operation that calculates by dividing bits of an input signal into bits equal to or greater than the number of bits of the input signal. The synchronization unit may be configured to synchronize signals used in a threshold implementation operation process based on the generated enable signal.