SBus Controller Interface for ASIC Test Efficiency
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing complexity of ASICs and the need for efficient testing methods are hindered by the lengthy scan chain tests, limited I/O pins, and the high cost associated with generating and regenerating test patterns for each design change, especially when testing disparate ASICs with shared support functions.
Innovation Solution
The introduction of a Serializer/De-serializer bus (SBus) with strategically located receivers allows for a standardized interface to access ASIC support functions via addresses, enabling the reuse of test commands across similar ASIC versions and independent testing of core logic and support functions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If scan chain testing is used to test ASIC core logic and support functions, then comprehensive fault coverage is achieved, but test time increases substantially due to serial bit-shifting of test patterns
Solution Approach 1:
The patent segments the testing process by introducing a scan controller that manages multiple scan chains independently. The scan controller divides the test pattern generation and application across multiple parallel scan chains, allowing simultaneous testing of different circuit segments. This segmentation enables parallel processing of test vectors, significantly reducing the overall test time while maintaining comprehensive fault coverage across all scan chains.
Solution Approach 2:
The scan controller acts as an intermediary between the test pattern generator and the scan chains. It manages the serial-to-parallel conversion of test patterns, controls the clocking of individual scan chains, and coordinates the capture and shift operations. This intermediary component enables efficient test pattern distribution and synchronization across multiple scan chains, reducing test time without compromising fault coverage.
2Adaptability or versatility
If the number of flip-flops in ASIC increases to meet design complexity requirements, then device functionality improves, but scan test length increases leading to higher testing costs
Solution Approach 1:
The patent divides the large number of flip-flops into multiple scan chains, each managed independently by the scan controller. This segmentation allows the testing system to handle large-scale ASIC designs by distributing the test workload across multiple smaller scan chains rather than using a single long scan chain. The result is improved testing efficiency and reduced test time while maintaining the ability to test all flip-flops in the complex ASIC design.
Solution Approach 2:
The scan controller dynamically manages the operation of multiple scan chains, enabling flexible configuration and control of scan chain lengths and operations. This dynamic control allows optimization of test patterns and clocking sequences to efficiently test large numbers of flip-flops, improving productivity despite the increased device complexity and functionality.
3Device complexity
If Serializer/De-serializers are added to ASIC architecture to reduce I/O pin requirements, then I/O pin count decreases, but the number of clock cycles needed to perform scan tests increases
Solution Approach 1:
The patent introduces multiple scan chains that can operate in parallel, segmenting the test data path to compensate for the reduced I/O pin count. By dividing the test pattern application across multiple scan chains, the system maintains efficient testing performance despite the increased clock cycles required per individual chain, achieving a balance between I/O constraints and test time.
Solution Approach 2:
The scan controller ensures continuous and efficient utilization of scan chains by managing the flow of test patterns and responses without idle cycles. This continuous operation maximizes the productivity of the available I/O pins and scan chains, reducing the total number of clock cycles needed despite the architectural constraints imposed by Serializer/De-serializers.
4Reliability
If test patterns are regenerated for each ASIC design change to ensure accurate fault testing, then test accuracy is maintained, but test generation time and cost increase significantly
Solution Approach 1:
The scan controller is designed with pre-configured control logic and state machines that automatically generate appropriate test sequences for different scan chain configurations. This preliminary preparation of control mechanisms allows rapid adaptation to design changes without requiring complete regeneration of test patterns, maintaining test accuracy while reducing generation time and cost.
Solution Approach 2:
The patent enables reuse of scan controller configurations and test sequences across different ASIC designs and design iterations. By copying and adapting proven test patterns and controller settings from previous designs, the system maintains test accuracy for new design changes while avoiding the time and cost of creating entirely new test patterns from scratch.
Data Source
AI summary
An application specific integrated circuit (ASIC) uses a dedicated interface between core logic and an independent Serializer/De-serializer bus (SBus) to provide SBus capabilities to the core logic. In addition to the dedicated interface, the ASIC includes a controller responsive to a set of signals and a plurality of receivers distributed about the SBus. Each of the receivers is responsive to a set of commands that can be reused to test logic and support functions across each revision of the ASIC as well as to test separate ASICs with similar arrangements of support functions without requiring the generation of a distinct scan vector to test the ASIC. Additional interfaces, such as an I.E.E.E. 1149.1 interface, further extend SBus capabilities to external test equipment.