SC-FDMA Signal Generation via Time-Domain Interpolation
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Solution Overview
Problem
Conventional SC-FDMA transmitters require significant processing power due to the implementation of DFT blocks, which is a scarce resource in battery-operated devices, and are restricted by the need for specific prime factors in mixed radix FFTs, complicating hardware implementations.
Innovation Solution
A method is introduced to generate SC-FDMA signals by performing a first interpolation operation on input symbols in the time domain to produce interpolated symbols, which are then mapped to orthogonal sub-carriers, potentially reducing the number of calculations and avoiding the need for DFTs, using techniques such as Nyquist interpolation and filter cascades.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If DFT blocks are implemented in conventional SC-FDMA transmitters, then SC-FDMA signal generation is achieved, but processing power requirements increase significantly
Solution Approach 1:
The patent extracts and removes the DFT block from the conventional SC-FDMA transmitter signal flow. By eliminating the DFT operation, the patent directly reduces the computational complexity and processing power requirements while maintaining the essential SC-FDMA signal generation functionality through alternative signal processing approaches.
Solution Approach 2:
The patent replaces the mechanical/DFT-based signal processing system with an alternative implementation that uses different mathematical operations. Specifically, it substitutes the DFT-based approach with a method that achieves the same signal generation goal through different computational mechanisms, thereby reducing processing power consumption.
2Use of energy by moving object
If mixed radix FFTs are used to reduce processing power, then processing power requirements decrease, but hardware implementation complexity increases due to restrictions on prime factors
Solution Approach 1:
The patent removes the mixed radix FFT component from the signal processing chain. By eliminating this complex component, it avoids the hardware implementation restrictions associated with prime factors while still achieving reduced processing power requirements through the overall signal processing method.
Solution Approach 2:
The patent segments the signal processing into distinct stages that can be independently implemented. By dividing the processing into manageable segments, it simplifies the hardware implementation requirements while maintaining efficiency, avoiding the need for complex mixed radix FFT structures.
3Reliability
If DFT-based methods are used for SC-FDMA modulation, then signal processing is achieved, but the number of multiplications and additions increases
Solution Approach 1:
The patent extracts and eliminates the DFT operation from the signal processing sequence. This removal directly reduces the number of multiplications and additions required, as DFT operations are computationally intensive. The patent maintains signal processing reliability through alternative methods that require fewer calculations.
Solution Approach 2:
The patent applies a partial processing approach that achieves the necessary signal processing functionality without performing all possible calculations. By using selective processing techniques, it reduces the total number of multiplications and additions while maintaining sufficient signal quality and processing reliability.
Data Source
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AI summary
A technique for generating a single carrier frequency division multiple access (SC-FDMA) signal is described, in which from a set of M input symbols a set of N output symbols (M < N) is generated. A method implementation of this technique comprises receiving a set of M input symbols in a time domain representation, subjecting the set of M input symbols to an interpolation operation in the time domain to obtain L interpolated samples (L ≤ N), mapping the interpolated symbols, or symbols derived from the interpolated symbols, to N orthogonal sub-carriers, and outputting N output symbols in a time domain representation.