SCA-Based Memory Controller with Parallel NAND Command Scheduling
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Solution Overview
Problem
Existing memory systems face inefficiencies in data transfer and storage due to limitations in command execution pipelines, particularly in non-volatile memory components like NAND flash, which hinder parallel processing and sequencing of commands.
Innovation Solution
Implementing a Separate Command Address (SCA)-based memory controller that utilizes two or more data path scheduler (DPS) request queues and a NAND flash controller (NFC) sequencer to convert high-level commands into SCA-based commands, enabling parallel scheduling and sequence execution compliant with the SCA protocol, thereby improving data processing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional memory controllers use single command execution pipeline, then device complexity is low, but data transfer efficiency and parallel processing capability are limited
Solution Approach 1:
The command execution pipeline is segmented into multiple independent paths: a first path for receiving high-level commands and a second path for converting them to SCA-based commands. Multiple DPS request queues (first, second, third queues) are created to handle different command types simultaneously, enabling parallel processing while maintaining manageable complexity through structured division of labor.
Solution Approach 2:
The patent introduces a new dimensional aspect by implementing multiple request queues (first, second, third DPS request queues) that operate in parallel. This allows commands to be processed through different pathways simultaneously, transforming a single-dimensional sequential execution model into a multi-dimensional parallel execution model, thereby improving productivity.
2Productivity
If multiple request queues are implemented for parallel command scheduling, then command processing efficiency improves, but device complexity increases
Solution Approach 1:
The request queue system is segmented into specialized queues: a first DPS request queue for certain command types, a second DPS request queue for other command types, and a third DPS request queue for additional parallel processing. Each queue is managed independently with specific functions, allowing parallel command processing while distributing management complexity across dedicated structures.
Solution Approach 2:
The NFC sequencer acts as an intermediary that receives commands from multiple DPS request queues and manages their conversion to SCA-based commands. This intermediary component coordinates the complexity of multiple queues by providing a unified interface for command conversion and sequence execution, reducing the overall system complexity burden.
3Productivity
If high-level commands are converted to SCA-based commands through multiple pipelines, then data processing efficiency improves, but conversion time and processing overhead increase
Solution Approach 1:
Commands are converted to SCA-based commands in advance through the second path before execution begins. The NFC sequencer performs this conversion preliminarily, preparing commands for efficient execution. This preliminary conversion action allows the actual data processing to proceed without delays, improving overall efficiency despite the conversion time required.
Solution Approach 2:
Multiple request queues operate continuously and in parallel, converting commands and preparing them for execution without interruption. The first, second, and third DPS request queues continuously receive and process high-level commands, converting them to SCA-based commands without idle time, thereby minimizing the impact of conversion time on overall processing efficiency.
Data Source
AI summary
The subject application relates to separate command address (SCA) protocol-based memory controllers. For instance, a method may include receiving, by a separate command address (SCA)-based memory controller, a plurality of commands, scheduling, by the SCA-based memory controller, the plurality of commands using two or more data path scheduler (DPS) request queues, converting the scheduled plurality of commands into SCA-based commands, selecting, from the scheduled SCA-based commands, one or more scheduled SCA-based commands for a sequence execution, and executing in sequence the selected one or more SCA-based commands using one or more logical units (LUNs) of a channel in a memory component.