Switched Capacitor Array Partial Readout for Low Dead Time
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Solution Overview
Problem
Switched capacitor array (SCA) circuits face significant dead-time during fast readout processes due to the need to read out all sampling cells, which limits their application in high channel density, low power, and high accuracy requirements, especially in particle physics experiments.
Innovation Solution
The implementation of a domino wave circuit with a series of double inverters generates a write signal for sampling cells, allowing for a stop circuit to receive trigger signals and generate a stop position pulse, enabling the readout of a subset of sampling cells, thereby reducing dead-time through a readout circuit that starts at the stop position.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If all sampling cells are read out sequentially, then complete waveform data is captured, but dead time increases significantly
Solution Approach 1:
The patent divides the 1024 sampling cells into multiple groups (e.g., 16 groups of 64 cells each). Instead of reading all cells sequentially, the system reads only the necessary groups containing signal information, thereby reducing dead time while maintaining complete waveform capture for relevant channels.
Solution Approach 2:
The system performs partial readout by selectively reading only those sampling cells that contain useful signal information, rather than reading all 1024 cells. This partial action approach reduces the readout time and dead time while still capturing the complete waveform data needed for analysis.
2Productivity
If high channel density is implemented, then more signals can be processed, but readout complexity and time increase
Solution Approach 1:
The patent merges multiple sampling channels into a shared readout path using multiplexers. Multiple channels share common readout circuitry and ADC resources, which reduces overall device complexity while maintaining high channel density. The time-division multiplexing allows efficient resource utilization across all 12 channels.
Solution Approach 2:
The readout circuitry is designed with universal functionality to handle multiple channels through time-division multiplexing. The same ADC and readout logic serve all 12 channels sequentially, eliminating the need for dedicated readout circuits for each channel and thereby reducing device complexity while maintaining high channel density.
3Measurement precision
If all 1024 sampling cells are read out, then complete time resolution is achieved, but readout speed decreases
Solution Approach 1:
The patent segments the 1024 sampling cells into functional groups and reads only the necessary segments containing signal information. This selective segment-based readout maintains the time resolution capability for relevant channels while significantly improving readout speed by avoiding unnecessary reads of empty or irrelevant cells.
Solution Approach 2:
The system performs preliminary identification of which sampling cells contain useful signal information before initiating the readout process. This preliminary action allows the system to prepare and execute readout only for necessary cells, thereby maintaining complete time resolution for signal-containing channels while improving overall readout speed.
Data Source
AI summary
A method relates to a technique for reducing the readout time of switched capacitor array circuitries. An implementation is a SCA chip capable of sampling 12 differential input channels at a sampling speed of 10 MSPS to 5 GSPS. The analog waveform can be stored in 1024 sampling cells per channel, and can be read out after sampling via a shift register. The write signal for the sampling cells is generated by a chain of inverters. The domino wave runs continuously until stopped. A read shift register clocks the contents of the sampling cells to outputs, where it can be digitized. It is possible to read out only a part of the waveform for reducing the digitization time. The high channel density, high analog bandwidth of 450 MHz, and low noise of 0.35 mV makes this chip suited for low power, high speed, high precision waveform digitizing.