Scalability Model for Multithreaded Processor Capacity Planning
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Solution Overview
Problem
Current capacity planning tools are inadequate for analyzing the performance of multithreaded, multicore, and multichip processor systems, as they fail to account for non-linear scalability effects and resource contention, leading to inefficient workload allocation and hardware upgrades in data centers.
Innovation Solution
A method is developed to gather CPU performance data and create scalability models that predict system performance by using discrete event simulation and queuing theory-based analysis, incorporating scalability factors for linear and exponential scaling across various processor configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional capacity planning tools are used to analyze multithreaded multicore systems, then the analysis process is simple and fast, but the accuracy of performance prediction is insufficient due to failure to account for non-linear scalability effects and resource contention
Solution Approach 1:
The patent segments the complex multithreaded multicore system into hierarchical levels (sockets, cores, threads, virtual processors) and models each level separately with its own scalability characteristics. This allows accurate capture of non-linear scalability effects at each level while keeping the overall model manageable through structured composition of individual level models.
Solution Approach 2:
The patent introduces scalability factors as intermediary parameters that mediate between the complex underlying hardware architecture and the simplified capacity planning analysis. These scalability factors capture the non-linear performance characteristics without requiring planners to understand the complex underlying mechanisms, thus improving accuracy while maintaining ease of use.
2Measurement precision
If detailed scalability modeling is implemented for multithreaded systems, then performance prediction accuracy improves, but the computational complexity and data collection requirements increase
Solution Approach 1:
The patent collects scalability data at each hierarchical level (socket, core, thread) separately rather than requiring complete system-wide measurements. This partial action approach allows accurate characterization of individual level behavior with manageable data collection efforts, which then compose to provide accurate overall system predictions without requiring exhaustive measurement of all possible configurations.
3Loss of energy
If server consolidation is pursued to reduce infrastructure costs, then space and power requirements decrease, but performance bottlenecks may occur due to resource contention that traditional tools cannot predict
Solution Approach 1:
The patent incorporates feedback mechanisms where scalability factors are measured from actual system behavior and used to predict performance under consolidation scenarios. This feedback loop allows identification of performance bottlenecks before they occur in production, enabling planners to adjust consolidation strategies to maintain reliability while achieving energy savings.
4Productivity
If multicore multithreaded processors are deployed to increase processing capacity, then system throughput improves, but resource contention increases leading to non-linear scalability that traditional models cannot capture
Solution Approach 1:
The patent changes the parameters used in capacity planning from simple linear assumptions to scalability factors that capture non-linear behavior. By transforming the modeling parameters to reflect actual multithreaded system characteristics, the tool maintains ease of operation while accurately predicting throughput and guiding workload allocation decisions.
Data Source
AI summary
A method for expressing a hierarchy of scalabilities in complex systems, including a discrete event simulation and an analytic model, for analysis and prediction of the performance of multi-chip, multi-core, multi-threaded computer processors is provided. Further provided is a capacity planning tool for migrating data center systems from a source configuration which may include source systems with multithreaded, multicore, multichip central processing units to a destination configuration which may include destination systems with multithreaded, multicore and multichip central processing units, wherein the destination systems may be different than the source systems. Apparatus and methods are taught for the assembling of and utilization of linear and exponential scalability factors in the capacity planning tool when a plurality of active processor threads populate processors with multiple chips, multiple cores per chip and multiple threads per core.