Scalable 3D System-in-Package Architecture for High Memory Density
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Solution Overview
Problem
Conventional systems-on-chip (SOCs) and application-specific integrated circuits (ASICs) face challenges in scaling to provide higher memory densities and bandwidths while maintaining efficiency.
Innovation Solution
A scalable system-in-package (SiP) architecture featuring a three-dimensional stack of memory dice and logic die, with networks-on-chip (NOCs) and memory controllers, allowing for customizable and configurable building blocks, engines, and communication interfaces to achieve high memory bandwidth and density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional SOCs and ASICs are scaled to provide higher memory densities and bandwidths, then memory capacity and data transmission speed are improved, but device complexity and manufacturing difficulty increase significantly
Solution Approach 1:
The system is divided into multiple independent memory dice (e.g., six memory dice) that are stacked vertically and connected via TSVs to a single logic die. Each memory die can be independently fabricated and tested before assembly, allowing high memory density to be achieved through modular stacking rather than scaling a single monolithic chip, thereby managing complexity through division.
Solution Approach 2:
The patent transitions from conventional two-dimensional planar integration to three-dimensional vertical stacking. Memory dice are stacked above the logic die with inter-layer connections via through-silicon vias (TSVs), enabling high memory density and bandwidth by utilizing the vertical dimension. This 3D architecture allows multiple memory dice to be connected to a single logic die, providing scalable memory capacity without increasing lateral device footprint or complexity.
2Quantity of substance
If memory density is increased in conventional SOCs, then storage capacity is improved, but manufacturing precision requirements become more stringent and difficult to achieve
Solution Approach 1:
The memory system is segmented into multiple separate memory dice that are fabricated independently using standard memory fabrication processes. Each memory die can be manufactured with conventional precision requirements, then assembled into a 3D stack with TSV connections. This segmentation allows high overall memory density to be achieved without requiring any single fabrication step to exceed conventional precision capabilities.
Solution Approach 2:
Memory dice are pre-fabricated, pre-tested, and pre-characterized independently before being assembled into the final 3D package. The TSV structures are formed and configured in advance during the memory die fabrication process. This preliminary preparation allows for quality control and precision verification at each stage before final assembly, reducing the precision burden on the final integration step.
3Speed
If higher memory bandwidth is provided through conventional scaling, then data transmission speed is improved, but power consumption increases
Solution Approach 1:
The patent implements a 3D stacked architecture where multiple memory dice are vertically stacked above the logic die with short TSV connection paths. This vertical integration dramatically reduces the physical distance between memory and logic, enabling high bandwidth memory interfaces with lower voltage swings and reduced dynamic power consumption compared to conventional lateral scaling approaches. The short interconnect lengths minimize RC delays and energy loss.
Solution Approach 2:
The TSV structures serve as efficient intermediary connection elements between memory dice and the logic die. These vertical vias provide low-resistance, low-capacitance interconnects that enable high-speed data transmission with minimal power consumption. The TSV-mediated connection architecture allows high bandwidth to be achieved without the excessive power consumption that would result from longer lateral interconnects in conventional 2D layouts.
Data Source
AI summary
A system-in-package architecture in accordance with aspects includes a logic die and one or more memory dice coupled together in a three-dimensional slack. The logic die can include one or more global building blocks and a plurality of local building blocks. The number of local building blocks can be scalable. The local building blocks can include a plurality of engines and memory controllers. The memory controllers can be configured to directly couple one or more of the engines to the one or more memory dice. The number and type of local building blocks, and the number and types of engines and memory controllers can be scalable.