Scalable Block Cipher Circuit for Power-Throughput Balance
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Solution Overview
Problem
Existing encryption and decryption processes are computationally intensive, consuming significant processing resources and power, especially in software implementations on general-purpose processors, which hampers performance and increases power consumption, particularly in high-throughput and high-clock-frequency applications.
Innovation Solution
A scalable block cipher circuit design that balances throughput with power consumption, implemented as a hardware logic circuit on an integrated circuit, featuring a pipelined architecture with adjustable depth and multiplexers for encryption and decryption operations, along with integrated key management functions, volatile memory for data and key storage, and a DMA engine for efficient data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If software implementation of encryption/decryption is used on general-purpose processors, then flexibility and ease of implementation are improved, but processing speed and power consumption are worsened
Solution Approach 1:
The patent replaces software-based encryption/decryption (mechanical system of general-purpose processor execution) with a dedicated hardware logic circuit implementation. This substitution provides specialized processing paths, parallel operation capabilities, and optimized logic gates that dramatically improve processing speed while maintaining encryption functionality.
Solution Approach 2:
The patent introduces a hardware logic circuit as an intermediary component between the processor and data storage, specifically designed to handle encryption/decryption operations. This intermediary provides a specialized processing layer that offloads computationally intensive cryptographic operations from the general-purpose processor, improving overall system performance.
2Adaptability or versatility
If software implementation of encryption/decryption is used on general-purpose processors, then adaptability is improved, but power consumption is worsened
Solution Approach 1:
The patent implements a scalable block cipher circuit with adjustable pipeline depth that can dynamically adapt to different throughput requirements. The circuit includes control logic that can modify the number of active pipeline stages based on performance needs, allowing the system to balance power consumption against processing speed by activating only the necessary number of pipeline stages.
Solution Approach 2:
The patent employs parameter changes by allowing the block cipher circuit to operate with variable pipeline depth and configurable security parameters. The circuit can adjust its operational characteristics (number of rounds, pipeline stages) to match the required security level and performance demands, optimizing power consumption for different application scenarios.
3Productivity
If hardware logic circuit with pipelined architecture is used, then processing throughput is improved, but circuit complexity is worsened
Solution Approach 1:
The patent divides the block cipher processing into discrete pipeline stages, with each stage handling a specific portion of the encryption/decryption process. This segmentation allows parallel processing of multiple data blocks simultaneously at different pipeline stages, dramatically improving throughput. The modular stage design also simplifies verification and testing compared to a monolithic circuit.
Solution Approach 2:
The patent implements a nested pipeline structure where multiple rounds of the block cipher are organized in nested pipeline stages. Each round contains nested operations (substitution, permutation, mixing) that are systematically arranged to enable parallel execution. This nesting approach maximizes throughput while maintaining organized circuit structure.
4Adaptability or versatility
If adjustable pipeline depth is implemented, then scalability and power efficiency are improved, but control logic complexity is worsened
Solution Approach 1:
The patent pre-configures multiple fixed pipeline depth options into the circuit design, allowing the system to select from predetermined scalability levels. This preliminary structuring enables quick adaptation to different performance requirements without requiring complex runtime reconfiguration logic, as the circuit is already prepared with multiple operational modes.
Data Source
AI summary
An integrated circuit for data encryption/decryption and secure key management is disclosed. The integrated circuit may be used in conjunction with other integrated circuits, processors, and software to construct a wide variety of secure data processing, storage, and communication systems. An embodiment of the integrated circuit includes a run-time scalable block cipher circuit, wherein the run-time scalable block cipher circuit is run-time scalable to balance throughput with power consumption.