Scalable Boolean Logic Optimization for Integrated Circuits
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Solution Overview
Problem
Existing Boolean optimization methods for integrated circuits (ICs) are limited by high computational cost, making them less scalable and less applicable in automated IC design, especially at advanced technology nodes where transistor scaling slows down.
Innovation Solution
The implementation of scalable Boolean techniques and systems that select the appropriate optimization engine based on circuit characteristics, using truth-tables, binary decision diagrams (BDDs), or satisfiability (SAT) solvers for efficient logic optimization, along with circuit partitioning and Boolean difference-based resubstitution frameworks to reduce computational overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If Boolean methods are used for logic optimization, then optimization quality is improved, but computational cost increases
Solution Approach 1:
The logic network is divided into smaller windows or partitions that can be processed independently using Boolean methods. This segmentation allows the expensive Boolean optimization to be applied only to manageable sub-problems rather than the entire circuit, reducing overall computational cost while maintaining optimization quality.
Solution Approach 2:
Different optimization methods are applied to different parts of the logic network based on their characteristics. Boolean methods are used locally in regions where they provide the most benefit, while simpler methods are used elsewhere, optimizing the trade-off between quality and computational cost.
2Measurement precision
If Boolean methods are used for logic optimization, then optimization quality is improved, but scalability deteriorates
Solution Approach 1:
By partitioning the logic network into smaller windows, the method enables Boolean optimization to scale to larger circuits. Each window can be processed independently using Boolean methods, and the results are combined to optimize the entire network, thus achieving both high optimization quality and scalability.
Solution Approach 2:
The optimization process dynamically adjusts the size and number of windows based on circuit characteristics. This dynamic adaptation allows the system to automatically scale the Boolean optimization approach to handle circuits of varying sizes and complexities while maintaining effective optimization quality.
3Use of energy by moving object
If partitioning techniques are applied to enable Boolean optimization, then computational cost is reduced, but optimization quality may deteriorate
Solution Approach 1:
The partitioning approach applies Boolean optimization to partial windows of the logic network rather than the entire circuit. This partial action reduces computational cost significantly, and the cumulative effect of optimizing each window contributes to overall optimization quality that approaches the result of optimizing the entire circuit.
Solution Approach 2:
The optimization results from multiple partitions or windows are merged to produce the final optimized logic network. By combining the benefits from each partition, the method achieves optimization quality comparable to global optimization while incurring only a fraction of the computational cost.
Data Source
AI summary
Techniques and systems for optimizing a logic network are described. Some embodiments automatically identify scenarios where Boolean methods are best driven by truth tables, binary decision diagrams (BDDs) or satisfiability (SAT). Some embodiments use circuit partitioning techniques that are based on hash-tables and topological sorting, and that are capable of grouping nodes with high simplification likelihood and still are able to efficiently scale to large circuits. Some embodiments feature a generalized resubstitution framework based on computing, and implementing, the Boolean difference between two nodes. Some embodiments include enhancements to (i) gradient-based and-inverter-graph (AIG) optimization, (ii) heterogeneous elimination for kerneling, and (iii) revisitation of maximum set of permissible functions (MSPF) computation with BDDs.