Scalable Circuit Verification via Segmented Evaluation and Canvassing
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Solution Overview
Problem
Existing methods for functional verification of integrated circuit designs are limited by the need for extensive data storage and signal value management, which can exceed typical storage device capacities and require complex interconnections, making them unsuitable for designs with many logic blocks and signals, and they do not easily accommodate incremental hardware additions or tolerate data arrival delays.
Innovation Solution
A scalable system comprising multiple evaluation units with evaluation processors and canvassing processors, using high-speed serial links for deterministic packet transfer and a compiler to manage data transfer and scheduling, ensuring efficient data handling and incremental scalability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a target design is partitioned into many combinational logic blocks connected by sequential elements with state tables evaluated and stored in multiple RASDs, then functional verification capability is improved, but device complexity and storage requirements increase beyond practical limits
Solution Approach 1:
The system divides the verification functionality into separate evaluation units, each handling a portion of the circuit design. Each evaluation unit contains evaluation processors that independently evaluate logic blocks and canvassing processors that manage data transfer, allowing the system to handle large designs by partitioning them into manageable segments without requiring a single complex storage system
Solution Approach 2:
The patent introduces canvassing processors as intermediary components between evaluation processors and RASDs. These canvassing processors act as mediators that manage data transfer, coordinate access to storage devices, and handle the complexity of data management, thereby reducing the overall system complexity while maintaining verification capability
2Adaptability or versatility
If logic blocks exceed the convenient width of typical RASDs or require more logic blocks than can be practically accommodated, then verification of larger designs is enabled, but storage device capacity and interconnection complexity increase
Solution Approach 1:
The system transitions from a single-dimension storage approach to a multi-dimensional architecture by distributing logic blocks across multiple evaluation units and RASDs. This dimensional expansion allows the system to accommodate designs that exceed the capacity of individual storage devices by organizing data and processing across multiple spatial dimensions
Solution Approach 2:
Evaluation units are designed as universal, multi-functional components that can handle various types of logic blocks and circuit designs. Each evaluation unit can independently process different portions of a design, allowing the same hardware architecture to be applied universally across designs of varying sizes and complexities without requiring proportional increases in storage capacity
3Productivity
If more evaluation processors are added to increase parallelism and verification speed, then productivity is improved, but the number of circuit signal values shared throughout the system increases
Solution Approach 1:
The system segments signal values and data transfers into localized units handled by individual evaluation processors and their associated canvassing processors. This segmentation reduces the need for global sharing of signal values across the entire system, as each evaluation unit manages its own data locally, thereby enabling increased parallelism without proportional increases in shared signal values
Data Source
AI summary
A scalable system for verifying electronic circuit designs in anticipation of fabrication by compiling a hardware description to instructions for canvassing processors and instructions for circuit evaluation processors which are scalably interconnected to provide simulation and emulation, having deterministically scheduled transfer of circuit signal values among the large number of circuit evaluation processors.