Scalable Crossbar Layout for Low-Delay NoC Routing
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Solution Overview
Problem
Traditional crossbar designs for Network-on-Chip (NoC) face scalability issues with increasing data bus width and number of ports, leading to quadratic scaling of propagation delay and power consumption, which degrades performance and power efficiency.
Innovation Solution
The crossbar circuits are rearranged such that each data bit is handled by a 1-bit crossbar circuit, aggregated to form a radix-p d-bit crossbar, with signals routed in an x-first and y-second manner, reducing interconnect length and broadcasting, resulting in linear scaling of power and delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional crossbar design is used with increased data bus width and number of ports, then throughput and connectivity are improved, but propagation delay and power consumption scale quadratically
Solution Approach 1:
The crossbar is segmented into multiple smaller crossbar units organized in a hierarchical structure. Instead of one large crossbar handling all ports and data bits, the system divides it into smaller blocks that can be managed independently, reducing the propagation delay within each segment while maintaining overall throughput.
Solution Approach 2:
The patent introduces a hierarchical dimension to the crossbar architecture, organizing crossbar units in multiple levels (e.g., local crossbars and global crossbars). This dimensional organization allows data to travel through shorter paths at lower levels before aggregating at higher levels, reducing overall propagation delay while maintaining connectivity.
2Productivity
If traditional crossbar design is used with increased data bus width and number of ports, then connectivity and throughput are improved, but power consumption scales quadratically
Solution Approach 1:
The crossbar is segmented into multiple smaller crossbar units organized in a hierarchical structure. Instead of one large crossbar handling all ports and data bits, the system divides it into smaller blocks that can be managed independently, reducing the propagation delay within each segment while maintaining overall throughput.
Solution Approach 2:
The patent introduces a hierarchical dimension to the crossbar architecture, organizing crossbar units in multiple levels (e.g., local crossbars and global crossbars). This dimensional organization allows data to travel through shorter paths at lower levels before aggregating at higher levels, reducing overall propagation delay while maintaining connectivity.
3Speed
If crossbar radix is increased for lower latency in Network-on-Chip, then communication speed is improved, but physical dimension and interconnection length grow
Solution Approach 1:
The crossbar is segmented into multiple smaller crossbar units organized in a hierarchical structure. Instead of one large crossbar handling all ports and data bits, the system divides it into smaller blocks that can be managed independently, reducing the propagation delay within each segment while maintaining overall throughput.
Solution Approach 2:
The patent introduces a hierarchical dimension to the crossbar architecture, organizing crossbar units in multiple levels (e.g., local crossbars and global crossbars). This dimensional organization allows data to travel through shorter paths at lower levels before aggregating at higher levels, reducing overall propagation delay while maintaining connectivity.
Data Source
AI summary
Described is an apparatus (e.g., a router) which comprises: multiple ports; and a plurality of crossbar circuits arranged such that at least one crossbar circuit receives all interconnects associated with a data bit of the multiple ports and is operable to re-route signals on those interconnects.