Scalable Data Processing System with Memory Fabric
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Solution Overview
Problem
Conventional data processing systems are inefficient and often unable to handle petabyte-scale data sets due to limitations in high bandwidth access, leading to inefficient analysis and processing of large data sets.
Innovation Solution
A scalable data processing system architecture that utilizes multiple interconnected CPU subsystems with a shared memory fabric, allowing parallel access to a large number of memory chips and enabling concurrent, multi-threaded applications through specialized system software and hardware components such as memory roots, branches, and leaves.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional data processing systems are used, then system complexity remains manageable, but bandwidth access to petabyte-scale data sets becomes insufficient
Solution Approach 1:
The system divides the data processing architecture into multiple CPU subsystems, each with its own memory controller, interconnected through a high-speed fabric. This segmentation allows each subsystem to independently access memory resources, collectively providing petabyte-scale bandwidth without requiring a single complex centralized system.
Solution Approach 2:
The patent introduces a multi-dimensional memory hierarchy with memory roots, branches, and leaves organized in a tree structure. This dimensional organization allows parallel access paths from multiple CPU subsystems to different memory regions, exponentially increasing total bandwidth access capacity while managing system complexity through hierarchical abstraction.
2Productivity
If multiple interconnected CPU subsystems are implemented, then parallel access to memory chips is enabled, but device complexity increases
Solution Approach 1:
The memory fabric and memory controller architecture are designed as universal, standardized interfaces that all CPU subsystems use. Each subsystem follows the same protocol and connection patterns, allowing the system to scale by simply adding more identical subsystems rather than designing increasingly complex unique architectures for each configuration.
Solution Approach 2:
The high-speed memory fabric acts as an intermediary layer between CPU subsystems and memory chips. This mediator handles the complexity of coordinating multiple access requests, managing memory allocation, and routing data flows, thereby shielding individual CPU subsystems from the full complexity of the distributed memory system while enabling high parallel throughput.
Data Source
AI summary
According to one embodiment, a data processing system includes a plurality of processing units, each processing unit having one or more processor cores. The system further includes a plurality of memory roots, each memory root being associated with one of the processing units. Each memory root includes one or more branches and a plurality of memory leaves to store data. Each of the branches is associated with one or more of the memory leaves and to provide access to the data stored therein. The system further includes a memory fabric coupled to each of the branches of each memory root to allow each branch to access data stored in any of the memory leaves associated with any one of remaining branches.