Scalable Entropy Source Circuit With Ring Topology for 100% Entropy

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Solution Overview

Problem

Existing entropy source (ES) solutions lack scalability and fail to produce 100% entropy across varying environmental conditions, leading to reduced performance and inefficiencies in generating cryptographic quality random numbers, especially with the rise of quantum computing threats.

Innovation Solution

A scalable entropy source circuit is developed, utilizing a bistable circuit, a first latch circuit, and a charge pump circuit to generate random bits and voltage adjustment signals, which can be instantiated multiple times to meet high data rate requirements while minimizing power and area, and includes a ring topology for enhanced scalability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If existing entropy source solutions are used, then area is minimized, but scalability is limited and 100% entropy cannot be produced across varying environmental conditions

Engineering Contradiction:
ImprovescalabilityVSAvoidcircuit structure
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The entropy source is divided into multiple identical entropy source circuits that can be instantiated in parallel. Each circuit independently generates entropy bits, and the outputs are combined through conditioning logic to achieve the required throughput and entropy quality, enabling scalability while maintaining manageable complexity per instance

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from a single entropy source instance to multiple parallel instances operating simultaneously. This dimensional expansion from 1D (single circuit) to 2D (matrix of circuits) enables scaling the total entropy output by adding more instances without increasing the complexity of individual circuits

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If DRBG is used to provide deterministic random numbers, then data rate is improved (up to 2 GB/s), but quantum safety is compromised

Engineering Contradiction:
Improvedata rateVSAvoidquantum safety
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The system uses feedback through conditioning circuits that monitor the entropy bitstream quality and adjust extraction parameters dynamically. This ensures that even as data rates increase, the entropy quality metrics are maintained to satisfy NIST SP 800-90B requirements, enabling both high throughput and quantum safety

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent adjusts extraction parameters and conditioning logic based on measured entropy quality metrics. By dynamically changing extraction ratios and conditioning strength according to environmental conditions and observed entropy quality, the system maintains quantum-safe entropy output at high data rates

Inventive Principle:
Principle #35Parameter changes

3Reliability

If NRBG is used to provide non-deterministic random numbers, then quantum safety is improved, but data rate is reduced (to 10 MB/s)

Engineering Contradiction:
Improvequantum safetyVSAvoiddata rate
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

Multiple entropy source circuits are merged in parallel, with their outputs combined through conditioning logic. This aggregation of multiple quantum-safe entropy sources achieves high data rates while maintaining the quantum safety property, as the combined output still derives from fundamental physical randomness

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The entropy source circuit is designed as a universal building block that can be instantiated in different quantities to meet varying data rate requirements. The same basic circuit structure serves multiple functions: generating entropy bits, providing quantum-safe randomness, and enabling scalable throughput by adjusting the number of instances

Inventive Principle:
Principle #6Universality (Multi-functionality)

4Productivity

If entropy source output rate is increased to 1.6 Gb/s, then data rate requirement is met, but entropy quality may be compromised without proper conditioning

Engineering Contradiction:
Improveentropy output rateVSAvoidentropy quality
Core Design Contradiction:
ProductivityVSMeasurement precision

Solution Approach 1:

Conditioning circuits continuously monitor entropy quality metrics and adjust extraction parameters in real-time based on feedback from quality measurements. This closed-loop control ensures that even at high output rates of 1.6 Gb/s, the entropy quality maintains NIST SP 800-90B compliance

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The system applies excessive conditioning and extraction scrutiny to ensure quality. By using conservative extraction ratios and rigorous conditioning logic that exceeds minimum requirements, the patent guarantees entropy quality even when operating at high throughput rates

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS20250219643A1Highly scalable entropy source
Publication Date: 2025.07.03 INTEL CORP
  • US20250219643A1 patent drawing
  • US20250219643A1 patent drawing
  • US20250219643A1 patent drawing

AI summary

An apparatus configured as an entropy source circuit includes a bistable circuit, a first latch circuit, a charge pump circuit, and an oscillator circuit. The bistable circuit generates random bits based on an input clock signal and a plurality of voltage adjustment signals. The first latch circuit is coupled to the bistable circuit and generates entropy bits based on the random bits. The charge pump circuit is coupled to the latch circuit and generates the plurality of voltage adjustment signals based on the entropy bits and a plurality of clock phases (e.g., a redistribute clock signal and a precharge clock signal). The entropy source circuit can be coupled in a ring topology with a plurality of other entropy source circuits, where the plurality of clock phases can be generated based on output clock signals received from at least one of the plurality of other entropy source circuits.