Scalable Fabric Test Engine for SoC IP Testing
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Solution Overview
Problem
The increasing complexity of System on a Chip (SoC) integration leads to proportional testing complexity, resulting in higher costs and 'test quality holes' due to the growing number of IP blocks, making it inefficient to scale testing with Moore's law for silicon density, and adding more product engineers to develop test content is not a viable solution.
Innovation Solution
A scalable and power-efficient scalable fabric test engine (SFTE) architecture that works as a plug-and-play mechanism on a primary scalable fabric and in tandem with secondary sideband fabrics, enabling IP-level and full-chip level testing operations by communicating with IP blocks and cores through addressable ports, using a split transaction protocol for maximum concurrency and supporting standard interfaces like IOSF, OCP, and AMBA.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of IP blocks is increased to improve SoC functionality and integration density, then the testing complexity increases proportionally, resulting in higher costs and test quality holes
Solution Approach 1:
The patent introduces an on-chip test controller as an intermediary component that mediates between external test equipment and multiple IP blocks. This controller provides a unified interface and automated test sequence management, reducing the complexity burden that would otherwise fall on external testing systems and engineers.
Solution Approach 2:
The test controller is integrated directly onto the chip, enabling the SoC to perform its own testing autonomously without requiring extensive external test equipment or manual intervention. This self-service capability reduces external testing complexity and allows for automated test execution across multiple IP blocks.
2Reliability
If more product engineers are added to develop test content, then test coverage may improve, but development costs and time increase
Solution Approach 1:
The integrated test controller provides automated test sequence generation and execution capabilities, reducing the manual effort required from engineers. The system can autonomously manage test campaigns across multiple IP blocks, improving test coverage without proportionally increasing engineering resources.
Solution Approach 2:
The test controller is designed as a universal platform that can handle various test types and scenarios across different IP blocks through a single integrated interface. This multi-functionality reduces the need for specialized test development for each IP block, improving overall development efficiency.
3Measurement precision
If traditional external testing methods are used for each IP block, then individual block testing is possible, but overall testing time and resource requirements increase
Solution Approach 1:
The patent merges multiple individual IP block testing operations into a single integrated on-chip test controller that can execute coordinated test sequences. This consolidation maintains the precision needed for individual block testing while reducing overall testing time by eliminating redundant setup and measurement operations.
Solution Approach 2:
The test controller enables continuous test execution across multiple IP blocks without requiring interruption for reconfiguration or external equipment setup. Test sequences can run continuously through different blocks, reducing idle time and accelerating the overall testing process while maintaining measurement precision.
Data Source
AI summary
An apparatus and method are described for a scalable testing agent. For example, one embodiment of a scalable test engine comprises: an input interface to receive commands and/or data from a processor core or an external test system, the commands and/or data to specify one or more test operations to be performed on one or more intellectual property (IP) blocks of a chip; a first circuit to establish communication with an IP block over an interconnect fabric, the first circuit to transmit the one or more test operations to the IP block responsive to the received commands and/or data, the IP block to process the test operations and generate results; and a second circuit to receive the results from the IP block over the interconnect fabric, the results to be provided from the second circuit to the processor core and/or the external test system for analysis.