Scalable FINFET Gate Structure with Inner Spacers
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Solution Overview
Problem
As fin field-effect transistor (FINFET) technology scales, challenges arise in reducing fin pitch and increasing fin height, leading to patterning and process difficulties, as well as increased parasitic capacitance due to taller gates.
Innovation Solution
The method involves patterning fins in a substrate, depositing conformal gate dielectric and sacrificial layers, replacing these with workfunction-setting metals, forming dielectric gates, and creating inner spacers to separate gates from source and drains, thereby minimizing capacitance and improving dimension control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If fin pitch is reduced to increase density, then device density is improved, but patterning and process challenges increase
Solution Approach 1:
The gate structure is segmented into multiple materials (semiconductor material, first dielectric material, second dielectric material) with different dielectric constants. This segmentation allows each layer to serve specific functions: the semiconductor gate provides channel control, the first dielectric reduces parasitic capacitance, and the second dielectric provides mechanical support, thereby enabling high density without compromising manufacturability
Solution Approach 2:
The patent changes the dielectric parameter (permittivity) by using materials with different dielectric constants in different gate regions. Low-k dielectric materials are used in regions where capacitance reduction is critical, while high-k or standard dielectric materials are used where mechanical strength is needed, thus resolving the contradiction between density and manufacturing ease
2Reliability
If fin height is increased to meet performance requirements, then device performance is improved, but parasitic capacitance increases due to taller gates
Solution Approach 1:
Different regions of the gate structure are assigned different dielectric materials based on their specific functional requirements. The semiconductor gate region uses low-k dielectric to minimize parasitic capacitance where electrical performance is critical, while other regions use different dielectric materials to maintain mechanical integrity and support the increased fin height, thus achieving both performance improvement and capacitance reduction
3Length of stationary object
If gate height is increased to support taller fins, then fin height capability is improved, but parasitic capacitance increases
Solution Approach 1:
The gate structure employs a composite material system combining semiconductor materials (for channel formation), first dielectric materials with low-k values (for parasitic capacitance reduction), and second dielectric materials (for mechanical support). This composite structure enables the gate to support taller fins while simultaneously minimizing parasitic capacitance through the strategic use of low-k dielectric materials in critical regions
Data Source
AI summary
Scalable device designs for FINFET technology are provided. In one aspect, a method of forming a FINFET device includes: patterning fins in a substrate which include a first fin(s) corresponding to a first FINFET device and a second fin(s) corresponding to a second FINFET device; depositing a conformal gate dielectric over the fins; depositing a conformal sacrificial layer over the gate dielectric; depositing a sacrificial gate material over the sacrificial layer; replacing the sacrificial layer with a first workfunction-setting metal(s) over the first fin(s) and a second workfunction-setting metal(s) over the second fin(s); removing the sacrificial gate material; forming dielectric gates over the first workfunction-setting metal(s), the second workfunction-setting metal(s) and the gate dielectric forming gate stacks; and forming source and drains in the fins between the gate stacks, wherein the source and drains are separated from the gate stacks by inner spacers. A FINFET device is also provided.